HCPL-0708

High Speed CMOS Optocoupler

Data Sheet

Description

Available in SO-8 package, the HCPL-0708 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of the HCPL-0708 are a high speed LED and a CMOS detector IC. The detector incorporates an integrated photodiode, a high-speed trans-impedance amplifier, and a voltage comparator with an output driver.

Functional Diagram

NC 1

ANODE

2

8 VDD

7 NC

Features

• +5 V CMOS compatibility

• 15 ns typical pulse width distortion

• 30 ns max. pulse width distortion

• 40 ns max. propagation delay skew

• High speed: 15 MBd

• 60 ns max. propagation delay

• 10 kV/

µ

s minimum common mode rejection

• –40 to 100

°

C temperature range

• Safety and regulatory approvals pending

– UL recognized

3750 V rms for 1 min. per UL 1577 for HCPL-0708

– CSA component acceptance Notice #5

– IEC/EN/DIN EN 60747-5-2 approved for HCPL-0708 Option 060

CATHODE 3

NC

4

TRUTH TABLE

LED

OFF

ON

VO, OUTPUT

H

L

6 VO

5

GND

Applications

• Scan drive in PDP

• Digital field bus isolation: DeviceNet, SDS, Profibus

• Multiplexed data transmission

• Computer peripheral interface

• Microprocessor system interface

• DC/DC converter

*A 0.1

µ

F bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Ordering Information

HCPL-0708 is UL Recognized with 3750 Vrms for 1 minute per UL1577.

-000E

HCPL-0708 -500E

-060E

-560E

Option

Part RoHS non RoHS

Number Compliant Compliant Package

no option

-500

-060

-560

SO-8

Surface Gull Tape UL 5000 Vrms/ IEC/EN/DIN

Mount Wing & Reel 1 Minute rating EN 60747-5-2 Quantity

X X X

100 per tube

1500 per reel

X X X

X

X

100 per tube

1500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.

Example 1:

HCPL-0708-500E to order product of Small Outline SO-8 package in Tape and Reel packaging and RoHS compliant.

Example 2:

HCPL-0708 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and

RoHS compliant will use ‘–XXXE.’

2

Package Outline Drawing

HCPL-0708 (Small Outline SO-8 Package)

LAND PATTERN RECOMMENDATION

8 7 6

XXXV

YWW

5

3.937 ± 0.127

(0.155 ± 0.005)

5.994 ± 0.203

(0.236 ± 0.008)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

PIN ONE

1

0.406 ± 0.076

(0.016 ± 0.003)

2 3 4

1.270

(0.050)

BSC

*

5.080 ± 0.127

(0.200 ± 0.005)

7°

0.64 (0.025)

45° X

0.432

(0.017)

7.49 (0.295)

1.9 (0.075)

3.175 ± 0.127

(0.125 ± 0.005)

0 ~ 7°

1.524

(0.060)

* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

5.207 ± 0.254 (0.205 ± 0.010)

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

0.305

(0.012)

MIN.

0.203 ± 0.102

(0.008 ± 0.004)

0.228 ± 0.025

(0.009 ± 0.001)

3

Solder Reflow Thermal Profile

300

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.

REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

PEAK

TEMP.

245°C

200

160°C

150°C

140°C

2.5°C ± 0.5°C/SEC.

30

SEC.

30

SEC.

PEAK

TEMP.

240°C

PEAK

TEMP.

230°C

SOLDERING

TIME

200°C

100

3°C + 1°C/–0.5°C

PREHEATING TIME

150°C, 90 + 30 SEC.

50 SEC.

ROOM

TEMPERATURE

0

0 50

Note: Non-halide flux should be used.

100 150

TIME (SECONDS)

200

TIGHT

TYPICAL

LOOSE

250

Recommended Pb-Free IR Profile tp

Tp

TL

Tsmax

Tsmin

260 +0/-5 °C

217 °C

RAMP-UP

3 °C/SEC. MAX.

150 - 200 °C ts

PREHEAT

60 to 180 SEC.

tL

TIME WITHIN 5 °C of ACTUAL

PEAK TEMPERATURE

20-40 SEC.

RAMP-DOWN

6 °C/SEC. MAX.

60 to 150 SEC.

25 t 25 °C to PEAK

TIME

NOTES:

THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.

Tsmax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used.

Regulatory Information

The HCPL-0708 has been approved by the following organizations:

UL

Recognized under UL 1577, component recognition program,

File E55361.

CSA

Approved under CSA Component

Acceptance Notice #5, File

CA88324.

IEC/EN/DIN EN 60747-5-2

Approved under:

IEC 60747-5-2:1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884

Teil 2):2003-01

(Option 060 only)

4

Insulation and Safety Related Specifications

Parameter

Minimum External Air

Gap (Clearance)

Symbol

L(I01)

Minimum External

Tracking (Creepage)

Minimum Internal Plastic

Gap (Internal Clearance)

L(I02)

Value

4.9

4.8

0.08

Tracking Resistance

(Comparative Tracking Index)

CTI

≥

175

Isolation Group IIIa

Volts

Units

mm mm mm

Conditions

Measured from input terminals to output terminals, shortest distance through air.

Measured from input terminals to output terminals, shortest distance path along body.

Insulation thickness between emitter and detector; also known as distance through insulation.

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered.

There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances.

Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

5

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)

Description

Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage

≤

150 V rms for rated mains voltage

≤

300 V rms for rated mains voltage

≤

450 V rms

Climatic Classification

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b†

V

IORM

x 1.875 = V

PR

, 100% Production

Test with t m

= 1 sec, Partial Discharge < 5 pC

Input to Output Test Voltage, Method a†

V

IORM

x 1.5 = V

PR

, Type and Sample Test, t m

= 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage†

(Transient Overvoltage, t ini

= 10 sec)

Safety Limiting Values

(Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.)

Case Temperature

Input Current

Output Power

Insulation Resistance at T

S

, V

10

= 500 V

I

Symbol

V

V

V

V

T

P

R

IORM

PR

PR

IOTM

S

S,INPUT

S,OUTPUT

IO

HCPL-0708 Option 060

I-IV

I-III

55/85/21

2

560

1050

840

4000

150

150

600

≥

10

9

Units

V peak

V peak

V peak

V peak

°

C mA mW

Ω

†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section

IEC/EN/DIN EN 60747-5-2, for a detailed description.

Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits.

Note: The surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter

Storage Temperature

Ambient Operating Temperature

[1]

Supply Voltages

Output Voltage

Average Output Current

Average Forward Input Current

Lead Solder Temperature

Solder Reflow Temperature Profile

Symbol

T

S

T

A

V

DD

Min.

–55

–40

0

Max.

125

+100

6

Units

°

C

°

C

Volts

V

O

I

O

–0.5

V

2

DD2

+0.5

Volts mA

I

F

20 mA

260

°

C for 10 sec., 1.6 mm below seating plane

See Solder Reflow Temperature Profile Section

Figure

Recommended Operating Conditions

Parameter

Ambient Operating Temperature

Supply Voltages

Input Current (ON)

6

Symbol

T

A

V

DD

I

F

Min.

–40

4.5

10

Max.

+100

5.5

16

Units

°

C

V mA

Figure

1, 2

Electrical Specifications

Over recommended temperature (T

A

= –40

°

C to +100

°

C) and 4.5 V

≤

V

DD

≤

5.5 V.

All typical specifications are at T

A

= 25

°

C, V

DD

= +5 V.

Parameter

Input Forward Voltage

Input Reverse

Breakdown Voltage

Symbol Min.

V

F

BV

R

1.3

5

Typ.

1.5

Max.

1.8

Units

V

V

Test Conditions

I

F

= 12 mA

I

R

= 10

µ

A

V

OH

4.0

4.8

V I

F

= 0, I

O

= –20

µ

A Logic High Output

Voltage

Logic Low Output

Voltage

V

OL

0.01

0.1

V I

F

= 12 mA, I

O

= 20

µ

A

Input Threshold Current I

Logic Low Output

Supply Current

TH

I

DDL

6.0

8.2

14.0

mA mA

I

OL

= 20

µ

A

I

F

= 12 mA

Logic High Output

Supply Current

I

DDH

4.5

11.0

mA I

F

= 0

2

4

Fig.

Notes

1

3

Switching Specifications

Over recommended temperature (T

A

= –40

°

C to +100

°

C) and 4.5 V

≤

V

DD

≤

5.5 V.

All typical specifications are at T

A

= 25

°

C, V

DD

= +5 V.

Parameter

Propagation Delay Time to Logic Low Output

Propagation Delay Time to Logic High Output t t

Symbol Min.

Typ.

Max.

Units Test Conditions

PHL

PLH

20

13

35

21

60

60 ns ns

I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels

I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels

Pulse Width

Pulse Width Distortion

PW 100

|PWD| 0 14 30

Propagation Delay Skew

Output Rise Time

(10 - 90%)

Output Fall Time

(90 - 10%)

Common Mode

Transient Immunity at

Logic High Output

Common Mode

Transient Immunity at

Logic Low Output t t t

PSK

R

F

|CM

|CM

H

L

|

|

10

10

20

25

15

15

40 ns ns ns ns

I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels

I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels

I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels

2

3 ns I

F

= 12 mA, C

L

= 15 pF

CMOS Signal Levels kV/

µ s V

CM

= 1000 V, T

A

= 25

°

C, 4

I

F

= 0 mA kV/

µ s V

I

F

CM

= 1000 V, T

= 12 mA

A

Fig.

Notes

5 1

5

= 25

°

C, 5

1

2

3

4

5

7

Package Characteristics

All Typicals at T

A

= 25

°

C.

Parameter

Input-Output Insulation

Input-Output Momentary

Withstand Voltage

Input-Output Resistance

Input-Output Capacitance

I

Symbol

V

I-O

ISO

Min.

3750

Typ.

10

12

0.6

Max.

1

Units

µ

A

Vrms

Test Conditions

45% RH, t = 5 s

V

T

A

I-O

= 3 kV dc,

= 25

°

C

RH

≤

50%, t = 1 min.,

T

A

= 25

°

C

V

I-O

= 500 V dc f = 1 MHz, T

A

= 25

°

C

R

I-O

C

I-O

Ω pF

Notes:

1. t

PHL

propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 V level of the falling edge of the V

O

signal. t

PLH

propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the V

O signal.

2. PWD is defined as |t

PHL

- t

PLH

|.

3. t

PSK

is equal to the magnitude of the worst case difference in t

PHL

and/or t

PLH

that will be seen between units at any given temperature within the recommended operating conditions.

4. CM

H

is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.

5. CM

L

is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.

8

1000

100

10

1.0

0.1

+

VF

–

IF

0.01

I F

0.001

1.1

1.2

1.3

1.4

1.5

VF – FORWARD VOLTAGE – V

1.6

Figure 1. Typical input diode forward characteristic.

6

5

8

7

VDD = 5.0 V

IOL = 20 µA

4

3

I th

2

-40 0 25 85

TA – TEMPERATURE – °C

100

Figure 2. Typical input threshold current vs.

temperature.

6.0

5.5

5.0

4.5

4.0

VDD = 5.0 V

I ddh

3.5

3.0

2.5

2.0

-40 0 25 85

TA – TEMPERATURE – °C

100

Figure 3. Typical logic high O/P supply current vs. temperature.

I ddl

6.5

6.0

5.5

5.0

4.5

4.0

8.0

7.5

7.0

VDD = 5.0 V

-40 0 25 85

TA – TEMPERATURE – °C

100

Figure 4. Typical logic low O/P supply current vs. temperature.

50

45

40

35

Tphl

VDD = 5.0 V

TA = 25 °C

30

25

20

15

Tplh

PWD

10

5

0

5 6 7 8 9 10 11 12 13 14

IF – PULSE INPUT CURRENT – mA

Figure 5. Typical switching speed vs. pulse input current.

9

Application Information

Bypassing and PC Board Layout

The HCPL-0708 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL-0708 uses high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs.

As shown in Figure 6, the only external component required for proper operation is the bypass capacitor. Capacitor values should be between 0.01

µ

F and

0.1

µ

F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 7 illustrates the recommended printed circuit board layout for the HPCL-0708.

VI

3

4

1

2

8

C

7 NC

6

5 GND

VDD

VO

C1, C2 = 0.01 µF TO 0.1 µF

Figure 6. Recommended printed circuit board layout.

VDD

VI

C2

VO

GND

C1, C2 = 0.01 µF TO 0.1 µF

Figure 7. Recommended printed circuit board layout.

Propagation Delay, Pulse-Width

Distortion and Propagation Delay

Skew

Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t

PLH

) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high.

Similarly, the propagation delay from high to low (t

PHL

) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See

Figure 8.

INPUT

VI

OUTPUT

VO

10% tPLH

90%

Figure 8.

10

50%

5 V CMOS

0 V tPHL

90%

10%

VOH

2.5 V CMOS

VOL

Pulse-width distortion (PWD) is the difference between t

PHL

and t

PLH

and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically,

PWD on the order of 20 - 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application.

Propagation delay skew, t

PSK

, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers.

Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t

PLH

or t

PHL

, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in

Figure 9, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t

PSK

is the difference between the shortest propagation delay, either t

PLH

or t

PHL

, and the longest propagation delay, either t

PLH

or t

PHL

.

As mentioned earlier, t

PSK

can determine the maximum parallel data transmission rate. Figure 10 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock.

VI

VO

50%

2.5 V,

CMOS tPSK

50%

VI

VO

2.5 V,

CMOS

Figure 9. Propagation delay skew waveform.

DATA

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK tPSK tPSK

Figure 10. Parallel data transmission example.

Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler.

Figure 10 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t

PSK

.

A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.

The HCPL-0708 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges.

11

For product information and a complete list of distributors, please go to our website:

www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.

Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0031EN

AV01-0582EN July 7, 2007