FIN24AC Datasheet by onsemi

Datasheet Feedback/Errors

— FAIRCHII—D — SEMCDNDUCTQR- Des’“

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

January 2007

FIN24AC Rev. 1.0.3

FIN24AC

22-Bit Bi-Directional Serializer/Deserializer

Features

■Low power for minimum impact on battery life

– Multiple power-down modes

– AC coupling with DC balance

■100nA in standby mode, 5mA typical operating

conditions

■Cable reduction: 25:4 or greater

■Bi-directional operation 50:7 reduction or greater

■Differential signaling:

– -90dBm EMI when using CTL in lab conditions

using a near field probe

– Minimized shielding

– Minimized EMI filter

– Minimum susceptibility to external interference

■Up to 22 bits in either direction

■Up to 20MHz parallel interface operation

■Voltage translation from 1.65V to 3.6V

■Ultra-small and cost-effective packaging

■High ESD protection: >8kV HBM

■Parallel I/O power supply (VDDP) range between

1.65V to 3.6V

Applications

■Micro-controller or pixel interfaces

■Image sensors

■Small displays

– LCD, cell phone, digital camera, portable gaming,

printer, PDA, video camera, automotive

General Description

The FIN24AC µSerDes™ is a low-power Serializer/

Deserializer (SerDes) that can help minimize the cost

and power of transferring wide signal paths. Through the

use of serialization, the number of signals transferred

from one point to another can be significantly reduced.

Typical reduction is 4:1 to 6:1 for unidirectional paths.

For bi-directional operation, using half duplex for multiple

sources, it is possible to increase the signal reduction to

close to 10:1. Through the use of differential signaling,

shielding and EMI filters can also be minimized, further

reducing the cost of serialization. The differential signal-

ing is also important for providing a noise-insensitive sig-

nal that can withstand radio and electrical noise sources.

Major reduction in power consumption allows minimal

impact on battery life in ultra-portable applications. A

unique word boundary technique assures that the actual

word boundary is identified when the data is deserial-

ized. This guarantees that each word is correctly aligned

at the deserializer on a word-by-word basis through a

unique sequence of clock and data that is not repeated

except at the word boundary. A single PLL is adequate

for most applications, including bi-directional operation.

Ordering Information

Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.

µSerDesTM is a trademark of Fairchild Semiconductor Corporation.

Order Number Package

Number Pb-Free Package Description

FIN24ACGFX BGA042 Yes 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),

JEDEC MO-195, 3.5mm Wide

FIN24ACMLX MLP040 Yes 40-Terminal Molded Leadless Package (MLP), Quad,

JEDEC MO-220, 6mm Square

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 2

Functional Block Diagram

Figure 1. Block Diagram

CKREF CKS0+

CKSI+

–

CKSI-

cksint

DSO+/DSI-

Serializer

Control

WORD CK

Generator

Freq.

Control Direction

Control

Power Down

Control

Control Logic

Word

Boundary

Generator

Serializer

Deserializer

Control

PLL

DSO-/DSI+

100Ω Gated

Termination

100Ω

Termination

DIRO

CKS0-

CKP

DIRI

STROBE

DP[21:22]

DP[23:24]

DP[1:20]

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 3

Terminal Description

Note:

1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device,

the serial connections properly align without the need for any traces or cable signals to cross. Other layout

orientations may require that traces or cables cross.

Terminal

Name I/O Type

Number of

Terminals Description of Signals

DP[1:20] I/O 20 LVCMOS Parallel I/O, direction controlled by DIRI pin

DP[21:22] I 2 LVCMOS Parallel Unidirectional Inputs

DP[23:24] O 2 LVCMOS Unidirectional Parallel Outputs

CKREF IN 1 LVCMOS Clock Input and PLL Reference

STROBE IN 1 LVCMOS Strobe Signal for Latching Data into the Serializer

CKP OUT 1 LVCMOS Word Clock Output

DSO+ / DSI–

DSO– / DSI+ DIFF-I/O 2 CTL Differential Serial I/O Data Signals(1)

DSO: Refers to output signal pair

DSI: Refers to input signal pair

DSO(I)+: Positive signal of DSO(I) pair

DSO(I)–: Negative signal of DSO(I) pair

CKSI+, CKSI– DIFF-IN 2 CTL Differential Deserializer Input Bit Clock

CKSI: Refers to signal pair

CKSI+: Positive signal of CKSI pair

CKSI–: Negative signal of CKSI pair

CKSO+, CKSO– DIFF-OUT 2 CTL Differential Serializer Output Bit Clock

CKSO: Refers to signal pair

CKSO+: Positive signal of CKSO pair

CKSO–: Negative signal of CKSO pair

S1 IN 1 LVCMOS Mode Selection terminals used to select

Frequency Range for the RefClock, CKREF

S2 IN 1

DIRI IN 1 LVCMOS Control Input

Used to control direction of Data Flow:

DIRI = “1” Serializer, DIRI = “0” Deserializer

DIRO OUT 1 LVCMOS Control Output

Inversion of DIRI

VDDP Supply 1 Power Supply for Parallel I/O and Translation Circuitry

VDDS Supply 1 Power Supply for Core and Serial I/O

VDDA Supply 1 Power Supply for Analog PLL Circuitry

GND Supply 0 Use Bottom Ground Plane for Ground Signals

UCCCCCCCCCC HUQUUUUU! mmmmmmmmmh :333333333

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 4

Connection Diagrams

Figure 2. Terminal Assignments for MLP (Top View)

Figure 3. Terminal Assignments for µBGA

DP[9]

DP[10]

DP[11]

DP[12]

DDP

CKP

DP[13]

DP[14]

DP[15]

DP[16]

DIRO

CKSO+

CDSO-

DSO+

DSI-

DSO-

DSI+

CKSI-

CKSI+

DIRI

DDS

DP[17]

DP[18]

DP[19]

DP[20]

DP[21]

DP[22]

DP[23]

DP[24]

DDA

DP[8]

DP[7]

DP[6]

DP[5]

DP[4]

DP[3]

DP[2]

DP[1]

STROBE

CKREF

(Top View)

1 2 3 4 5 6

Pin Assignments

1234 5 6

A DP[9] DP[7] DP[5] DP[3] DP[1] CKREF

B DP[11] DP[10] DP[6] DP[2] STROBE DIRO

C CKP DP[12] DP[8] DP[4] CKSO+ CKSO-

D DP[13] DP[14] VDDP GND DSO- / DSI+ DSO+ / DSI-

E DP[15] DP[16] GND VDDS CKSI+ CKSI-

F DP[17] DP[18] DP[21] VDDA S2 DIRI

J DP[19] DP[20] DP[22] DP[23] DP[24] S1

FIN24AC Rev. 1.0.3 5

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Control Logic Circuitry

The FIN24AC has the ability to be used as a 24-bit Seri-

alizer or a 24-bit Deserializer. Pins S1 and S2 must be

set to accommodate the clock reference input frequency

range of the serializer. Table 1 shows the pin program-

ming of these options based on the S1 and S2 control

pins. The DIRI pin controls whether the device is a serial-

izer or a deserializer. When DIRI is asserted LOW, the

device is configured as a deserializer. When the DIRI pin

is asserted HIGH, the device is configured as a serial-

izer. Changing the state on the DIRI signal reverses the

direction of the I/O signals and generates the opposite

state signal on DIRO. For unidirectional operation, the

DIRI pin should be hardwired to the HIGH or LOW state

and the DIRO pin should be left floating. For bi-

directional operation, the DIRI of the master device is

driven by the system and the DIRO signal of the master

is used to drive the DIRI of the slave device.

Serializer/Deserializer with Dedicated I/O

Variation

The serialization and deserialization circuitry is setup for

24 bits. Because of the dedicated inputs and outputs,

only 22 bits of data are ever serialized or deserialized.

Regardless of the mode of operation, the serializer is

always sending 24 bits of data and two boundary bits

and the deserializer is always receiving 24 bits of data

and two word boundary bits. Bits 23 and 24 of the serial-

izer always contain the value of zero and are discarded

by the deserializer. DP[21:22] input to the serializer is

deserialized to DP[23:24] respectively.

Turn-Around Functionality

The device passes and inverts the DIRI signal through

the device asynchronously to the DIRO signal. Care

must be taken during design to ensure that no contention

occurs between the deserializer outputs and the other

devices on this port. Optimally the peripheral device driv-

ing the serializer should be in a HIGH-impedance state

prior to the DIRI signal being asserted.

When a device with dedicated data outputs turns from a

deserializer to a serializer, the dedicated outputs remain

at the last logical value asserted. This value only changes

if the device is once again turned around into a deserial-

izer and the values are overwritten.

Power-Down Mode: (Mode 0)

Mode 0 is used for powering down and resetting the

device. When both of the mode signals are driven to a

LOW state, the PLL and references are disabled, differen-

tial input buffers are shut off, differential output buffers are

placed into a HIGH-impedance state, LVCMOS outputs

are placed into a HIGH-impedance state, LVCMOS

inputs are driven to a valid level internally, and all internal

circuitry is reset. The loss of CKREF state is also enabled

to ensure that the PLL only powers up if there is a valid

CKREF signal.

In a typical application, signals do not change states other

than between the desired frequency range and the power-

down mode. This allows for system-level power-down

functionality to be implemented via a single wire for a

SerDes pair. The S1 and S2 selection signals that have

their operating mode driven to a “logic 0” should be hard-

wired to GND. The S1 and S2 signals that have their

operating mode driven to a “logic 1” should be connected

to a system level power-down signal.

Table 1. Control Logic Circuitry

Mode

Number S2 S1 DIRI Description

0 0 0 x Power-Down Mode

1 0 1 1 24-Bit Serializer, 2MHz to 5MHz CKREF

0 1 0 24-Bit Deserializer

2 1 0 1 24-Bit Serializer, 5MHz to 15MHz CKREF

1 0 0 24-Bit Deserializer

3 1 1 1 24-Bit Serializer, 10MHz to 20MHz CKREF

1 1 0 24-Bit Deserializer

FIN24AC Rev. 1.0.3 6

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Serializer Operation Mode

The serializer configurations are described in the following sections. The basic serialization circuitry works essentially

the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the

STROBE signal or not. When the CKREF equals STROBE, the CKREF and STROBE signals have an identical fre-

quency of operation, but may or may not be phase aligned. When CKREF does not equal STROBE, each signal is dis-

tinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never

be a lower frequency than STROBE.

The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve

lock prior to any valid data being sent. The CKREF signal can be used as the data

STROBE signal, provided that data can be ignored during the PLL lock phase.

Once the PLL is stable and locked, the device can begin to capture and serialize

data. Data is captured on the rising edge of the STROBE signal and serialized.

The serialized data stream is synchronized and sent source synchronously with a

bit clock with an embedded word boundary. When in this mode, the internal dese-

rializer circuitry is disabled; including the serial clock, serial data input buffers, the

bi-directional parallel outputs, and the CKP word clock. The CKP word clock is

driven HIGH.

Figure 4. Serializer Timing Diagram (CKREF equals STROBE)

If the same signal is not used for CKREF and STROBE, the CKREF signal must

be run at a higher frequency than the STROBE rate to serialize the data correctly.

The actual serial transfer rate remains at 26 times the CKREF frequency. A data

bit value of zero is sent when no valid data is present in the serial bit stream. The

operation of the serializer otherwise remains the same.

The exact frequency that the reference clock needs is dependent upon the stabil-

ity of the CKREF and STROBE signal. If the source of the CKREF signal imple-

ments spread spectrum technology, the maximum frequency of this spread

spectrum clock should be used in calculating the ratio of STROBE frequency to

the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-

cycle variation, the maximum cycle-to-cycle time needs to be factored into the

selection of the CKREF frequency.

Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE)

WORD n-1

WORD n-2 WORD n-1 WORD n

DPI[1:24]

CKREF

DSO

CKS0

b24 b25 b26 b1b2b3b4b1b2b3b4b5

b22 b23 b24 b25 b26

WORD n+1WORD n

WORD n-1

WORD n-1 WORD n

No Data

CKREF

DP[1:24]

DSO

CKS0

STROBE

b1b2b3b1b2b3

b4b5b6b7b22 b23 b24 b25 b26

WORD n+1

WORD n

Serializer Operation: (Figure 4)

MODE 1, 2, or 3

DIRI = 1,

CKREF = STROBE

Serializer Operation: (Figure 5),

DIRI = 1,

CKREF does not = STROBE

FIN24AC Rev. 1.0.3 7

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Serializer Operation Mode (Continued)

A third method of serialization can be accomplished with a free running bit clock

on the CKSI signal. This mode is enabled by grounding the CKREF signal and

driving the DIRI signal HIGH.

At power-up, the device is configured to accept a serialization clock from CKSI. If

a CKREF is received, this device enables the CKREF serialization mode. The

device remains in this mode even if CKREF is stopped. To re-enable this mode,

the device must be powered down and powered back up with a “logic 0” on

CKREF.

Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)

WORD n-1

WORD n-1 WORD n

No DataNo Data

DP[1:24]

DSO

CKS0

CKSI

STROBE

b1b2b3b1b2b3

b4b5b6b7b22 b23 b24 b25 b26

WORD n+1

WORD n

Serializer Operation: (Figure 6),

DIRI = 1,

No CKREF

RDCDRSDRéngéim ---------- m es—p i%a X

FIN24AC Rev. 1.0.3 8

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Deserializer Operation Mode

The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI

clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer

source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer

device used in generating the serial data and clock signals that are inputs to the deserializer.

When operating in this mode, the internal serializer circuitry is disabled; including the parallel data input buffers. If there

is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 =

1), all deserializer output data pins are driven LOW until valid data is passed through the deserializer.

When the DIRI signal is asserted LOW, the device is configured as a deserializer.

Data is captured on the serial port and deserialized through use of the bit clock

sent with the data. The word boundary is defined in the actual clock and data sig-

nal. Parallel data is generated at the time the word boundary is detected. The fall-

ing edge of CKP occurs approximately six bit times after the falling edge of CKSI.

The rising edge of CKP goes high approximately 13 bit times after CKP goes

LOW. The rising edge of CKP is generated approximately 13 bit times later. When

no embedded word boundary occurs, no pulse is generated on CKP and CKP

remains HIGH.

Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)

The logical operation of the deserializer remains the same if the CKREF is equal

in frequency to the STROBE or at a higher frequency than the STROBE. The

actual serial data stream presented to the deserializer, however, differs because it

has non-valid data bits sent between words. The duty cycle of CKP varies based

on the ratio of the frequency of the CKREF signal to the STROBE signal. The fre-

quency of the CKP signal is equal to the STROBE frequency. The falling edge of

CKP will occurs six bit times after the data transition. The LOW time of the CKP

signal is equal to half (13 bit times) of the CKREF period. The CKP HIGH time is

equal to STROBE period – half of the CKREF period. Figure 8 is representative of

a waveform that could be seen when CKREF is not equal to STROBE. If CKREF

is significantly faster, additional non-valid data bits occur between data words.

Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)

WORD n-1 WORD n+1WORD n

WORD n-2

DP[1:24]

CKPO

CKSI

DSI

WORD n

WORD n-1

WORD n-1 WORD n+1WORD n

bjbj+1 bj+13 bj+14

6 bit times

13 bit times

00 00

WORD n-2

DP[1:24]

CKPO

CKSI

DSI

WORD n

WORD n-1

Deserializer Operation: DIRI = 0

(Serializer Source:

CKREF = STROBE)

Deserializer Operation: DIRI = 0

(Serializer Source:

CKREF does not = STROBE)

FIN24AC Rev. 1.0.3 9

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Embedded Word Clock Operation

The FIN24AC sends and receives serial data source

synchronously with a bit clock. The bit clock has been

modified to create a word boundary at the end of each

data word. The word boundary has been implemented

by skipping a low clock pulse. This appears in the serial

clock stream as 3 consecutive bit times where signal

CKSO remains HIGH.

To implement this sort of scheme, two extra data bits are

required. During the word boundary phase, the data tog-

gles either HIGH-then-LOW or LOW-then-HIGH depen-

dent upon the last bit of the actual data word. Table 2

provides some examples of the actual data word and the

data word with the word boundary bits added. Note that

a 24-bit word is extended to 26-bits during serial trans-

mission. Bit 25 and Bit 26 are defined with-respect-to Bit

24. Bit 25 is always the inverse of Bit 24, and Bit 26 is

always the same as Bit 24. This ensures that a “0” →

“1” and a “1” → “0” transition always occurs during the

embedded word phase where CKSO is HIGH.

The serializer generates the word boundary data bits

and the boundary clock condition and embeds them into

the serial data stream. The deserializer looks for the end

of the word boundary condition to capture and transfer

the data to the parallel port. The deserializer only uses

the embedded word boundary information to find and

capture the data. These boundary bits are stripped prior

to the word being sent out the parallel port.

LVCMOS Data I/O

The LVCMOS input buffers have a nominal threshold

value equal to half VDDP. The input buffers are only oper-

ational when the device is operating as a serializer.

When the device is operating as a deserializer, the inputs

are gated off to conserve power.

The LVCMOS 3-STATE output buffers are rated for a

source/sink current of 2mA at 1.8V. The outputs are

active when the DIRI signal is asserted LOW. When the

DIRI signal is asserted HIGH, the bi-directional LVCMOS

I/Os are in a HIGH-Z state. Under purely capacitive load

conditions, the output swings between GND and VDDP.

Unused LVCMOS input buffers must be tied off to either a

valid logic LOW or a valid logic HIGH level to prevent

static current draw due to a floating input. Unused LVC-

MOS output should be left floating. Unused bi-directional

pins should be connected to GND through a high-value

resistor. If a FIN24AC device is configured as an unidi-

rectional serializer, unused data I/O can be treated as

unused inputs. If the FIN24AC is hardwired as a deseri-

alizer, unused data I/O can be treated as unused out-

puts.

Figure 9. LVCMOS I/O

Differential I/O Circuitry

The FIN24AC employs FSC proprietary CTL I/O technol-

ogy. CTL is a low-power, low-EMI, differential swing I/O

technology. The CTL output driver generates a constant

output source and sink current. The CTL input receiver

senses the current difference and direction from the out-

put buffer to which it is connected. This differs from

LVDS, which uses a constant current source output, but

a voltage sense receiver. Like LVDS, an input source ter-

mination resistor is required to properly terminate the

transmission line. The FIN24AC device incorporates an

internal termination resistor on the CKSI receiver and a

gated internal termination resistor on the DS input

receiver. The gated termination resistor ensures proper

termination regardless of direction of data flow. The rela-

tively greater sensitivity of the current sense receiver of

CTL allows it to work at much lower current drive and a

much lower voltage.

During power-down mode, the differential inputs are dis-

abled and powered down and the differential outputs are

placed in a HIGH-Z state. CTL inputs have an inherent

fail-safe capability that supports floating inputs. When

the CKSI input pair of the serializer is unused, it can reli-

ably be left floating. Alternately both of the inputs can be

connected to ground. CTL inputs should never be con-

nected to VDD. When the CKSO output of the deserial-

izer is unused, it should be allowed to float.

From

Deserializer

Serializer

From

Control

DP[n]

Table 2. Word Boundary Data Bits

24-Bit Data Words 24-Bit Data Word with Word Boundary

Hex Binary Hex Binary

3FFFFFh 0011 1111 1111 1111 1111 1111b 1FFFFFFh 01 1111 1111 1111 1111 1111 1111b

155555h 0101 0101 0101 0101 01010 0101b 1155555h 01 0101 0101 0101 0101 0101 0101b

xxxxxxh 0xxx xxxx xxxx xxxx xxxx xxxxb 1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb

FIN24AC Rev. 1.0.3 10

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Figure 10. Bi-Directional Differential I/O Circuitry

PLL Circuitry

The CKREF input signal is used to provide a reference to

the PLL. The PLL generates internal timing signals capa-

ble of transferring data at 26 times the incoming CKREF

signal. The output of the PLL is a bit clock that is used to

serialize the data. The bit clock is also sent source syn-

chronously with the serial data stream.

There are two ways to disable the PLL: by entering the

Mode 0 state (S1 = S2 = 0) or by detecting a LOW on

both the S1 and S2 signals. When any of the other

modes are entered by asserting either S1 or S2 HIGH

and by providing a CKREF signal. The PLL powers up

and goes through a lock sequence. Wait the specified

number of clock cycles prior to capturing valid data into

the parallel port. When the µSerDes chipset transitions

from a power-down state (S1, S2 = 0, 0) to a powered

state (example S1, S2 = 1, 1), CKP on the deserializer

transitions LOW for a short duration, then returns HIGH.

Following this, the signal level of the deserializer at CKP

corresponds to the serializer signal levels.

An alternate way of powering down the PLL is by stop-

ping the CKREF signal either HIGH or LOW. Internal cir-

cuitry detects the lack of transitions and shuts the PLL

and serial I/O down. Internal references,however, are not

disabled, allowing the PLL to power-up and re-lock in a

lesser number of clock cycles than when exiting Mode 0.

When a transition is seen on the CKREF signal, the PLL

is reactivated.

–

DS+

DS-

Gated

Termination

(DS Pins Only)

From

Serializer

Deserializer

From

Control

FIN24AC Rev. 1.0.3 11

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Application Mode Diagrams Unidirectional Data Transfer

Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer

Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode.

In Master Operation, the device:

1. Is configured as a serializer at power-up based on the

value of the DIRI signal.

2. Accepts CKREF_M word clock and generates a bit

clock with embedded word boundary. This bit clock is

sent to the slave device through the CKSO port.

3. Receives parallel data on the rising edge of

STROBE_M.

4. Generates and transmits serialized data on the

DS signals source synchronously with CKSO.

5. Generates an embedded word clock for each strobe

signal.

In Slave Operation, the device:

1. Is configured as a deserializer at power-up based on

the value of the DIRI signal.

2. Accepts an embedded word boundary bit clock on

CKSI.

3. Deserializes the DS data stream using the CKSI input

clock.

4. Writes parallel data onto the DP_S port and generates

the CKP_S. CKP_S is only generated when a valid

data word occurs.

Figure 12. Unidirectional Serializer and Deserializer

–

CKREF_M

CKSO CKSI

CKP_S

DP[1:12]_S

Serializer

Control

BIT CK

Gen.

PLL

Master Device Operating as a Serializer

DIR = “1”

S2 = S1 = “0”

Slave Device Operating as a Deserializer

DIR = “0”

S2 = S1 = “0”

Deserializer

Control

Work CK

Gen

Serializer Deserializer

STROBE_M

DP[1:12]_M

CKREF

Note:

Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer.

Receiving

Unit

STROBE

DP[21:22]

CKSI

DS DP[23:24]

DP[1:20]

CNTL[0:1]

DATA [0:19]

CNTL[0:1]

DATA [0:19] DP[1:20]

DIRI

VDD

DIRI

CKSO CKP

FIN24AC FIN24AC

Sending

Unit

REFCK

FIN24AC Rev. 1.0.3 12

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Figure 13. Multiple Units, Unidirectional Signals in Each Direction

Figure 13 shows a half-duplex connectivity diagram. This

connectivity allows for two unidirectional data streams to

be sent across a single pair of SerDes devices. Data is

sent on a frame-by-frame basis. For this mode, there

must be some synchronization between when the cam-

era sends its data frame and when the LCD sends its

data. One option is to have the LCD send data during the

camera blanking period. External logic may be needed

for this mode of operation.

Devices alternate frames of data controlled by a direction

control and a direction sense. When DIRI on the right-

hand FIN24AC is HIGH, data is sent from the camera to

the camera interface at the base. When DIRI on the

right-hand FIN24AC goes LOW, is sent from the base-

band process to the LCD. The direction is then changed

at DIRO on the right-hand FIN24AC, indicating to the

left-hand FIN24AC to change direction. Data is sent

from the base LCD unit to the LCD. The DIRO pin on the

left-hand FIN24AC is used to indicate to the base control

unit that the signals are changing direction and the LCD

is available to receive data. DIRI on the right-hand

FIN24AC could typically use a timing reference signal,

such as VSYNC from the camera interface, to indicate

direction change. A derivative of this signal may be

required to make sure that no data is lost in the final data

transfer.

Flex Circuit Design Guidelines

The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex

cable. The following best practices should be used when developing the flex cabling or Flex PCB:

■Keep all four differential wires the same length.

■Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.

■Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.

■Do not place test points on differential serial wires.

■Use differential serial wires a minimum of 2cm away from the antenna.

CKREF

Base

Unit

LCD

Camera

Disable

STROBE

DP[21:22]

CKSI

CKSO

DP[23:24]

DP[1:20]

DP[21:22]

STROBE

CKREF

VSYNC/HSYNC

PwrDwn

Camera/LCD Select

DP[1:20]

LCD

Unit

Camera

Unit

GPIO

DIRI DIRI

CKSO CKP

CKSI

DIRO DIRO

FIN24AC FIN24AC

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 13

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Unit

VDD Supply Voltage -0.5 +4.6 V

ALL Input/Output Voltage -0.5 +4.6 V

LVDS Output Short-Circuit Duration Continuous

TSTG Storage Temperature Range -65 +150 °C

TJMaximum Junction Temperature +150 °C

TLLead Temperature (Soldering, 4 seconds) +260 °C

ESD Human Body Model, 1.5kΩ, 100pF All Pins > 2 kV

CKSO, CKSI, DSO to GND > 7.5 kV

Symbol Parameter Min. Max. Unit

VDDA, VDDS Supply Voltage 2.5 2.9 V

VDDP Supply Voltage 1.65 3.6 V

TAOperating Temperature -30 +70 °C

VDDA-PP Supply Noise Voltage 100 mVp-p

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 14

DC Electrical Characteristics

Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.

Notes:

2. Typical Values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into device

and negative values means current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified

(except ΔVOD and VOD).

3. VGO is the difference in device ground levels between the CTL driver and the CTL receiver.

Symbol Parameter Test Conditions Min. Typ.(2) Max. Unit

LVCMOS I/O

VIH Input High Voltage 0.65 x VDDP VDDP

VIL Input Low Voltage GND 0.35 x VDDP V

VOH Output High Voltage IOH = –2.0 mA

VDDP = 3.3 ± 0.3

0.75 x VDDP VVDDP = 2.5 ± 0.2

VDDP = 1.8 ± 0.15

VOL Output Low Voltage IOL = 2.0 mA

VDDP = 3.3 ± 0.3

0.25 x VDDP VVDDP = 2.5 ± 0.2

VDDP = 1.8 ± 0.15

IIN Input Current VIN = 0V to 3.6V –5.0 5.0 µA

DIFFERENTIAL I/O

IODH Output High Source

Current VOS = 1.0V, Figure 14 –1.75 mA

IODL Output Low Sink Current VOS = 1.0V, Figure 14 0.950 mA

IOZ Disabled Output Leakage

Current

CKSO, DSO = 0V to VDDS,

S2 = S1 = 0V ±0.1 ±5.0 µA

IIZ Disabled Input Leakage

Current

CKSI, DSI = 0V to VDDS,

S2 = S1 = 0V ±0.1 ±5.0 µA

VICM Input Common Mode Range VDDS = 2.775 ± 5% VGO + 0.80 V

VGO Input Voltage Ground

Off-set Relative to Driver(3) See Figure 15 0 V

RTRM CKSI Internal Receiver

Termination Resistor

VID = 50mV, VIC = 925mV, DIRI =

0, | CKSI+ – CKSI- | = VID 80.0 100 120 Ω

RTRM DSI Internal Receiver,

Termination Resistor

VID = 50mV, VIC = 925mV, DIRI =

0, | DSI+ – DSI- | = VID 80.0 100 120 Ω

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 15

Power Supply Currents

AC Electrical Characteristics

Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.

Symbol Parameter Test Conditions Min. Typ. Max. Units

IDDA1 VDDA Serializer Static

Supply Current

All DP and Control Inputs at 0V or VDD,

No CKREF, S2 = 0, S1 = 1, DIR = 1 450 µA

IDDA2 VDDA Deserializer Static

Supply Current

All DP and Control Inputs at 0V or VDD,

No CKREF, S2 = 0, S1 = 1, DIR = 0 550 µA

IDDS1 VDDS Serializer Static Supply

Current

All DP and Control Inputs at 0V or VDD,

No CKREF, S2 = 0, S1 = 1, DIR = 1 4.0 mA

IDDS2 VDDS Deserializer Static Supply

Current

All DP and Control Inputs at 0V or VDD,

No CKREF, S2 = 0, S1 = 1, DIR = 0 4.5 mA

IDD_PD VDD Power-Down Supply Current

IDD_PD = IDDA + IDDS + IDDP S1 = S2 = 0, All Inputs at GND or VDD 0.1 µA

IDD_SER1

26:1 Dynamic Serializer Power

Supply Current

IDD_SER1 = IDDA + IDDS + IDDP

CKREF = STROBE

DIRI = H

See Figure 16

S2 = L

S1 = H

2MHz 9.0

5MHz 14.0

S2 = H

S1 = L

5MHz 9.5

15MHz 17.0

S2 = H

S1 = H

10MHz 11.0

20MHz 15.5

IDD_DES1

1:26 Dynamic Deserializer Power

Supply Current

IDD_DES1 = IDDA + IDDS + IDDP

CKREF = STROBE

DIRI = L

See Figure 16

S2 = L

S1 = H

2MHz 5.5

5MHz 6.0

S2 = H

S1 = L

5MHz 4.0

15MHz 5.5

S2 = H

S1 = H

10MHz 7.5

20MHz 10.0

IDD_SER2

26:1 Dynamic Serializer Power

Supply Current

IDD_SER2 = IDDA + IDDS + IDDP

NO CKREF

STROBE → Active

CKSI = 15X Strobe

DIRI = H, See Figure 16

2MHz 8.0

5MHz 8.5

10MHz 10.0

15MHz 12.0

Symbol Parameter Test Conditions Min. Typ.(4) Max. Units

SERIALIZER INPUT OPERATING CONDITIONS

tTCP CKREF Clock Period

(2MHz–20MHz)

See Figure 20

CKREF = STROBE

S2 = 0 S1 = 1 200 T 500 ns

S2 = 1 S1 = 0 66.0 200

S2 = 1 S1 = 1 50.0 100

fREF CKREF Frequency Relative to

Strobe Frequency

CKREF

does not equal

STROBE

S2 = 0 S1 = 1 1.1 x fST 5.0 MHz

S2 = 1 S1 = 0 15.0

S2 = 1 S1 = 1 20.0

tCPWH CKREF Clock High Time 0.2 0.5 T

tCPWL CKREF Clock Low Time 0.2 0.5 T

tCLKT LVCMOS Input Transition

Time

See Figure 20 90.0 ns

tSPWH STROBE Pulse Width

HIGH/LOW

See Figure 20

4) / 26 (T

22)

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 16

Notes:

4. Typical Values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into

device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise

specified (except ΔVOD and VOD).

5. Skew is measured form either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).

Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.

6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the

state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based

on the operating mode of the device.

7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock

remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total

measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects.

8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP

occurs approximately eight bit times after a data transition or six bit times after the falling edge of CKSO. Variation of

the data with respect of the CKP signal is due to internal propagation delay differences of the data and CKP path and

propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer, the

CKP signal does not maintain a 50% duty cycle. The low time of CKP remains 13 bit times.

fMAX Maximum Serial Data Rate CKREF x 26 S2 = 0 S1 = 1 52.0 130 Mb/s

S2 = 1 S1 = 0 130 390

S2 = 1 S1 = 1 260 520

tSTC DP(n) Setup to STROBE DIRI = 1 2.5 ns

tHTC DP(n) Hold to STROBE See Figure 9 (f = 5MHz) 2.0 ns

fREF CKREF Frequency Relative to

Strobe Frequency

CKREF Does Not Equal STROBE 1.1 x

fSTROBE

20.0 MHz

SERIALIZER AC ELECTRICAL CHARACTERISTICS

tTCCD Transmitter Clock Input to

Clock Output Delay

See Figure 23, DIRI = 1,

CKREF = STROBE

33a + 1.5 35a + 6.5 ns

tSPOS CKSO Position Relative to DS See Figure 26(5) –50.0 250 ps

PLL AC ELECTRICAL CHARACTERISTICS

tTPLLS0 Serializer PLL Stabilization

Time

See Figure 22 200 µs

tTPLLD0 PLL Disable Time Loss of

Clock

See Figure 27 30.0 µs

tTPLLD1 PLL Power-Down Time See Figure 28(6) 20.0 ns

DESERIALIZER INPUT OPERATION CONDITIONS

tS_DS Serial Port Setup Time,

DS-to-CKSI

See Figure 25(7) 1.4 ns

tH_DS Serial Port Hold Time,

DS-to-CKS

See Figure 25(7) –250 ps

DESERIALIZER AC ELECTRICAL CHARACTERISTICS

tRCOP Deserializer Clock Output

(CKP OUT) Period

See Figure 21 50.0 T 500 ns

tRCOL CKP OUT Low Time See Figure 21 (Rising Edge Strobe)

Serializer Source STROBE = CKREF

where a = (1/f) / 26(8)

13a-3 13a+3 ns

tRCOH CKP OUT High Time 13a-3 13a+3 ns

tPDV Data Valid to CKP LOW See Figure 21 (Rising Edge Strobe)

where a = (1/f) / 26(8) 8a-6 8a+1 ns

tROLH Output Rise Time

(20% to 80%)

CL = 5pF, See Figure 18 2.5 ns

tROHL Output Fall Time

(80% to 20%)

2.5 ns

Symbol Parameter Test Conditions Min. Typ.(4) Max. Units

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 17

Control Logic Timing Controls

Note:

9. Deserializer Enable Time includes the amount of time required for internal voltage and current references to stabilize.

This time is significantly less than the PLL lock time and does not impact overall system startup time.

Capacitance

Symbol Parameter Test Conditions Min. Typ. Max. Units

tPHL_DIR,

tPLH_DIR Propagation Delay

DIRI-to-DIRO DIRI LOW-to-HIGH or HIGH-to-LOW 17.0 ns

tPLZ, tPHZ Propagation Delay

DIRI-to-DP DIRI LOW-to-HIGH 25.0 ns

tPZL, tPZH Propagation Delay

DIRI-to-DP DIRI HIGH-to-LOW 25.0 ns

tPLZ, tPHZ Deserializer Disable Time:

S0 or S1 to DP DIRI = 0,

S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29 25.0 ns

tPZL, tPZH Deserializer Enable Time:

S0 or S1 to DP DIRI = 0,(9)

S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 29 2.0 µs

tPLZ, tPHZ Serializer Disable Time:

S0 or S1 to CKSO, DS DIRI = 1,

S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28 25.0 ns

tPZL, tPZH Serializer Enable Time:

S0 or S1 to CKSO, DS DIRI = 1,

S1(2) and S2(1) = LOW-to-HIGH, Figure 28 65.0 ns

Symbol Parameter Test Conditions Min. Typ. Max. Units

CIN Capacitance of Input Only Signals,

CKREF, STROBE, S1, S2, DIRI DIRI = 1, S1 = S2 = 0,

VDD = 2.5V 2.0 pF

CIO Capacitance of Parallel Port Pins DP1:12 DIRI = 1, S1 = S2 = 0,

VDD = 2.5V 2.0 pF

CIO-DIFF Capacitance of Differential I/O Signals DIRI = 0, S1 = S2 = 0,

VDD = 2.775V 2.0 pF

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 18

AC Loading and Waveforms

Figure 14. Differential CTL Output DC Test Circuit Figure 15. CTL Input Common Mode Test Circuit

Figure 16. “Worst-Case” Serializer Test Pattern

Figure 17. CTL Output Load and Transition Times Figure 18. LVCMOS Output Load

and Transition Times

Input

DS+

DS-

RL/2

VOD

VOS

–

DUT DUT

VGO

100Ω Termination +

–

Note:

The “worst-case” test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference

frequency, unless otherwise specified. Maximum power is measured at the maximum V

values. Minimum values are measured at the minimum V

values.

Typical values are measured at V

= 2.5V.

666h

11 11 11100 0 0 0 0

DP[1:12]

CKREF

CKS0-

CKS0+

DS+

DS-

666h999h

TLH

DIFF

= (DS+) – (DS-)

DIFF

20% 20%

80% 80%

DS+

DS-

5 pF 100Ω

–

THL

ROLH

20%

DPn

20%

80% 80%

5pF 1000Ω

ROHL

FIN24AC Rev. 1.0.3 19

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms (Continued)

Figure 19. Serial Setup and Hold Time Figure 20. LVCMOS Clock Parameters

Setup:

STROBE

DP[1:12]

STROBE

tSTC

tHTC

Data

DP[1:12]

Setup Time

Hold Time

MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”

CKREF

CLKT

90% 90%

10% 10%

50% 50%

CLKT

TCP

CPWH

CPWL

Figure 21. Deserializer Data Valid Window Time

and Clock Output Parameters

Figure 22. Serializer PLL Lock Time

CKP

DP[1:12]

PDV

Data

Data Valid

EN_DES = “1”, CKSI, and DSI are valid signals.

CKP 50% 75% 50%

25%

RCOP

RCOH

RCOL

Setup:

CKS0

CKREF

S1 or S2

VDD/VDDA

tTPLS0

Note: CKREF signal is free running.

Figure 23. Serializer Clock Propagation Delay Figure 24. Deserializer Clock Propagation Delay

STROBE

CKS0-

CKS0+

TCCD

DD/2

DIFF = 0

Note: STROBE = CKREF

CKSI-

CKSI+

CKP

RCCD

DD/2

DIFF

= 0

FIN24AC Rev. 1.0.3 20

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms (Continued)

Figure 25. Differential Input Setup and Hold Times Figure 26. Differential Output Signal Skew

CKSI-

CKSI+

DSI-

DSI+

H_DS

S_DS

VDIFF=0

VDIFF=0 VID/2

CKSO-

CKSO+

DSO-

DSO+

SK(P-P)

DIFF

= 0

DIFF

= 0

Note: Data is typically edge aligned with the clock.

Figure 27. PLL Loss of Clock Disable Time Figure 28. PLL Power-Down Time

CKS0

CKREF

TPPLD0

Note: CKREF Signal can be stopped either HIGH or LOW.

CKS0

S1 or S2

tTPPLD1

Figure 29. Serializer Enable and Disable Time Figure 30. Deserializer Enable and Disable Times

DS+,CKS0+

HIGH-Z

DS-,CKS0-

S1 or S2

PLZ(HZ)

PZL(ZH)

Note: CKREF must be active and PLL must be stable.

S1 or S2

PLZ(HZ)

PZL(ZH)

Note: If S1(2) transitioning, S2(1) must = 0 for test to be valid.

4k r—+ ,f “, » 000639000000: o e a {,9 e ﬂ L 4 $ —p

FIN24AC Rev. 1.0.3 21

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Tape and Reel Specification

Dimensions are in millimeters unless otherwise noted.

BGA Embossed Tape Dimension

Note:

10. A0, B0, and K0 dimensions are determined with

respect to the EIA/JEDEC RS-481 rotational and

lateral movement requirements (see sketches A, B,

and C).

User Direction of Feed

Package

±0.1 B0

±0.1 D

±0.05 D1

Min. E

±0.1 F

±0.1 K0

±0.1 P1

Typ. P0

Typ. P2

±0/05 T

Typ. TC

±0.005 W

±0.3 WC

Typ.

3.5 x 4.5 TBD TBD 1.55 1.5 1.75 5.5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3

Shipping Reel Dimension

10° maximum component rotation

Sketch C (Top View)

Component lateral movement

Typical component

cavity center line

1.0mm

maximum

W1 Measured at Hub

Dia A

max

Dia D

min

B Min

Dia C

Dia N

See detail AA

DETAIL AA

W2 max Measured at Hub

1.0mm

maximum

Typical component

center line

10° maximum

Sketch B (Top View)

Component Rotation

Sketch A (Side or Front Sectional View)

Component Rotation

Tape

Width Dia A

Max. Dim B

Min. Dia C

+0.5/–0.2 Dia D

Min. Dim N

Min. Dim W1

+2.0/–0 Dim W2

Max. Dim W3

(LSL–USL)

8 330 1.5 13.0 20.2 178 8.4 14.4 7.9 ~ 10.4

12 330 1.5 13.0 20.2 178 12.4 18.4 11.9 ~ 15.4

16 330 1.5 13.0 20.2 178 16.4 22.4 15.9 ~ 19.4

H, . 000639600000: Z) G) (+2 s99 w. —> \L A?

FIN24AC Rev. 1.0.3 22

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Tape and Reel Specification (Continued)

Dimensions are in millimeters unless otherwise noted.

MLP Embossed Tape Dimension

Note:

11. Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement

requirements (see sketches A, B, and C).

Package

±0.1 B0

±0.1 D

±0.05 D1

Min. E

±0.1 F

±0.1 K0

±0.1 P1

Typ. P0

Typ. P2

±0/05 T

Typ. TC

±0.005 W

±0.3 WC

Typ.

5 x 5 5.35 5.35 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3

6 x 6 6.30 6.30 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3

Tape

Width Dia A

Max. Dim B

Min. Dia C

+0.5/–0.2 Dia D

Min. Dim N

Min. Dim W1

+2.0/–0 Dim W2

Max. Dim W3

(LSL–USL)

8 330 1.5 13 20.2 178 8.4 14.4 7.9 ~ 10.4

12 330 1.5 13 20.2 178 12.4 18.4 11.9 ~ 15.4

16 330 1.5 13 20.2 178 16.4 22.4 15.9 ~ 19.4

User Direction of Feed

Shipping Reel Dimension

10° maximum component rotation

Sketch C (Top View)

Component lateral movement

Typical component

cavity center line

1.0mm

maximum

W1 Measured at Hub

Dia A

max

Dia D

min

B Min

Dia C

Dia N

See detail AA

DETAIL AA

W2 max Measured at Hub

1.0mm

maximum

Typical component

center line

10° maximum

Sketch B (Top View)

Component Rotation

Sketch A (Side or Front Sectional View)

Component Rotation

TOP VTEW /7 i ‘ 4 fr H§5+L5L5ga i,“ :0 Z D 5-. @nzaiuosj J 0 same mug o o 0 NOTES. 0 A. CONEORMS TO JEDEC REGTSTRATTON M07195, 0 E. DTMENSTONS ARE TN MTLLTMETERS. C. DTMENSTONS AND TOLERANCES PER ASME YT4,5M, 1994 D‘ STATTSTTCAL TOLERANCTNG FOR REFERENCE REFER TO MAX DTMENSTON FOR QA TNSPECTTON E. LAND PAWERN RECOMENDATTON PER TP077351 TABLET4715 LAND PATTERN NAME PER TABLE 37M). BGA50P+6X7742 BGA42ArevB Figure 31. Fb-Free, 42-Ball, Ullra Small Scale Ball Grid Array (USS-BGA OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO @ 2005 Fammu Semiconductor Curpuvahan FTNEAAC Rev 10 3 23

FIN24AC Rev. 1.0.3 23

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Physical Dimensions

Dimensions are in millimeters unless otherwise noted.

Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide

BOTTOM VIEW

3.50

4.50 0.5

0.5

3.0

2.5

Ø0.3±0.05

SEATING PLANE 0.23±0.05

0.45±0.05

(0.75)

(0.5)(0.35)

(0.6)

0.08 C

0.10 C

0.89±0.082

1.00 MAX

0.21±0.04

(QA CONTROL VALUE)

0.10 C

0.15 C A B

0.05 C

X42

TERMINAL

A1 CORNER

INDEX AREA

0.2+0.1

-0.0

LAND PATTERN

RECOMMENDATION

(2x) E- C E rm BO) 7 + — ' D D H H H [I H D J :1 :1 PM on \DEMT\ :I :I \O 53 MN I: :1 I: :1 Top “w (2x) 5 ms 0 I: :1 ”7W ‘7 MW E E :1 :1 80 W :1 ‘ :1 mm- L (n m) m 02mm , mm HUN __5J V mm: 0.23 MAX» v owwr— ~— ME 5qu vwEw m v 4.20 RECOMMENDED LAND PATTERN t WD :1 B B [:1 CI (DATUM E)77 El PW Fl ‘0 ‘ El :I n 3 [U U] D J] [I [I [I [I D m BOTTOM VIEw NOTES: “ OPHONAL MN ONE \DENWER A. CONFORMS TO JEDEC REG‘STRATION M07220, VAR‘AT‘ON WJJDrZ W‘TH EXCEPTION THIS IS A SAWN VERS‘ON. E D‘MENS‘ONS ARE \N M‘LLIMETERS C. D‘MENS‘ONS AND TOLERANCES PER D. LAND PAWERN PER \PC SMJEZ FABR‘CAT‘ON AND ASSEMBLY TOLERANCES 0F O,‘ MM APPUED WW‘DTH REDUCED TO AVOID SOLDER BR‘DGING. O, D‘MENS‘ONS ARE NOT \NCLUS‘VE OF BURRS, MOLD FLASH. NOR T‘E BAR PROTRUS‘ONS, MLP4OArev2 Figure 32. Fb-Free, KID-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-ZZO, 6mm Sq @ 2005 Emma Semiconductor Curpuvahan www HNzAAc Rev 10 3 24

FIN24AC Rev. 1.0.3 24

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

Physical Dimensions (Continued)

Dimensions are in millimeters unless otherwise noted.

Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square

(DATUM A)

TRADEMARKS The IollowIng are regIsIered and unregistered Irademarks Fairchild Semiconductor owns or Is authorized Io use and IS not intended to be an exhaustive list OI all such trademarks. ACExW FACT QuieISerIesW 00xTM SILENT SWITCHERE UrIIFETW AclIveArrayW GIobalOpIoisolatorW OCXPro'M SMART STARTW vcx W Boiiomlessm GT0W OPTOLOGIC® SPMW Wire'M EuIId n Nuw‘M HISeC'M OPTOPLANAR v Sieauhw CooIFETW IECVM PACMAN'M SuperFETW CROSSVOL 7"M i-Lo'M ROP‘M SuperSOTWJ DOMEW IrnpiredDrsoonneeI’M Power247’w SUperSOTWeG EcoSPARK'” InIeIIIMAxw PowerEdge w SuperSOT'Wﬁ EECMOSW ISOPLANARm PowerSever‘M SyncFETTM Ensignam LIuIeFETTM PowerTrench® TCMW FACTa MICROCOUPLER’V‘ QFET® TInyBoost FAST® MIcroFIETm QSW TInyBuckTM FASTr'M MIeroPakW QT OproeIeerroniesN TInyPWMTM FPSTM MICROWIRE'M Quiet SerIes" TIhyPowerT" FRFET'M MSX'I' RapIdCOnﬁgure'M TInyLOgIC® MS>

FIN24AC 22-Bit Bi-Directional Serializer/Deserializer

FIN24AC Rev. 1.0.3 25

FIN24AC Datasheet by onsemi

INFORMATION

HELP

CONTACT US

FOLLOW US