FIN1022 Datasheet by ON Semiconductor

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September 2001

Revised December 2001

FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

FIN1022

2 X 2 LVDS High Speed Crosspoint Switch

General Description

This non-blocking 2x2 crosspoint switch has a fully differ-

ential input to output data path for low noise generation and

low pulse width distortion. The device can be used as a

high speed crosspoint switch, 2:1 multiplexer, 1:2 demulti-

plexer or 1:2 signal splitter. The inputs can directly interface

with LVDS and LVPECL levels.

Features

■Low jitter, 800 Mbps full differential data path

■Worst case jitter of 190ps

with PRBS = 223 − 1 data pattern at 800 Mbps

■Rail-to-rail common mode range is 0.5V to 3.25V

■Worst case power dissipation is less than 126 mW

■Open-circuit fail safe protection

■Fast switch time of 1.1 ns typical

■35 ps typical pin channel to channel skew

■3.3V power supply operation

■Non-blocking switch

■LVDS receiver inputs accept LVPECL signals directly

■7.5 kV HBM ESD protection

■16-lead SOIC package and TSSOP package

■Inter-operates with TIA/EIA 644-1995 specification

■See the Fairchild Interface Solutions web page for cross

reference information:

www.fairchildsemi.com/products/interface/lvds.html

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number Package Number Package Description

FIN1022M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

FIN1022MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

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Connection Diagram Pin Descriptions

Function Table

O = OPEN L / O = LOW or OPEN H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance

Function Diagrams

Pin Name Description

RIN0+, RIN1+LVDS non-inverting data inputs

RIN0−, RIN1−LVDS inverting data inputs

DOUT0+, DOUT1+LVDS non-inverting data outputs

DOUT0−, DOUT1−LVDS inverting data outputs

EN0LVTTL input for enabling DOUT0+/DOUT0−

EN1LVTTL input for enabling DOUT1+/DOUT1−

SEL0LVTTL input for selecting RIN0+/RIN0− or

RIN1+/RIN1− for output DOUT0+/DOUT0−

SEL1LVTTL input for selecting RIN0+/RIN0− or

RIN1+/RIN1− for output DOUT1+/DOUT1−

VCC Power Supply

GND Ground

Inputs Outputs Mode

SEL0SEL1EN0EN1DOUT0+DOUT0−DOUT1+DOUT1−

L / O L / O H H RIN0+RIN0−RIN0+RIN0−1:2 Splitter

L / OHHHR

IN0+RIN0−RIN1+RIN1−Repeater

H L / O H H RIN1+RIN1−RIN0+RIN0−Switch

HHHHR

IN1+RIN1−RIN1+RIN1−1:2 Splitter

X L / O L / O H Z Z RIN0+RIN0−DOUT0 Disabled

XHL / OHZZR

IN1+RIN1−DOUT0 Disabled

L / O X H L / O RIN0+RIN0−ZZD

OUT1 Disabled

H X H L / O RIN1+RIN1−ZZD

OUT1 Disabled

XXL / OL / OZZZZD

OUT0 and DOUT1 Disabled

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Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings”: are those values beyond which

damage to the device may occur. The databook specifications should be

met, without exception, to ensure that the system design is reliable over its

power supply, temperature and output/input loading variables. Fairchild

does not recommend operation of circuits outside databook specification.

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified (Note 2)

Note 2: This part will only function with datasheet specification when a resistive load is applied to the driver outputs.

Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.

Supply Voltage (VCC)−0.3V to +4.6V

DC Input Voltage (VIN)−0.3V to +4.6V

DC Output Voltage (VOUT)−0.3V to +4.6V

Driver Short Circuit Current (IOSD) Continuous

Storage Temperature Range (TSTG)−65°C to +150°C

Max Junction Temperature (TJ)150°C

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

Supply Voltage (VCC) 3.0V to 3.6V

Input Voltage (VIN) 0 to VCC

Operating Temperature (TA)−40°C to +85°C

Electrostatic Discharge

(HBM 1.5 kΩ, 100 pF) >7500V

Electrostatic Discharge

(MM 0Ω, 100 pF) >300V

Symbol Parameter Test Conditions Min Typ Max Units

(Note 3)

LVDS Differential Driver Characteristics

VOD Output Differential Voltage RL = 75 Ω, See Figure 3 270 365 475

mVRL = 75 Ω, See Figure 3 285 365 440

TA = 25°C and VCC = 3.3V

∆VOD VOD Magnitude Change from RL = 75 Ω, See Figure 3 35 mV

Differential LOW-to-HIGH

VOS Offset Voltage See Figure 3 1.0 1.2 1.45 V

∆VOS Offset Magnitude Change from See Figure 3 35 mV

Differential LOW-to-HIGH

IOZD Disabled Output Leakage Current VOUT = 3.6V or GND, Driver Disabled ±10 µA

IOFF Power-Off Current VCC = 0V, VIN or VOUT = 3.6V or 0V ±20 µA

IOS Short Circuit Output Current VOUT = 0V, Driver Enabled −10 mA

VOUTx+ = 0V, VOUTx− = 0V, Driver Enabled −10

LVDS Differential Receiver Characteristics

VTH Differential Input Threshold HIGH VIC = 0.05V or 1.2V or 3.25V 100 mV

VTL Differential Input Threshold LOW VCC = 3.3V −100

VIC Input Common Mode Voltage 0.05 3.25 V

IIND Input Current (Differential Inputs) VIN = GND ±20 µA

VIN = VCC ±20

LVTTL Control Characteristics

VIH Input High Voltage 2 V

VIL Input Low Voltage 0.8 V

IIN Input Current VIN = 3.6V or GND ±20 µA

Device Characteristics

VIK Input Clamp Voltage IIK = −18 mA −1.5 V

IPU/PD Output Power-Up/Power-Down VCC = 0V to 1.5V ±10 µA

High Z Leakage Current

CIN Input Capacitance 4.5 pF

COUT Output Capacitance 4.5 pF

ICC Power Supply Current No Load, All Drivers Enabled 35 mA

RL = 75 Ω, All Drivers Enabled 35 mA

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AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 4: All typical values are at TA = 25°C and with VCC = 3.3V.

Note 5: Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same VCC and temperature condi-

tions.

Symbol Parameter Test Conditions Min Typ Max Units

(Note 4)

tPLHD Differential Output Propagation Delay 0.7 1.6 ns

LOW-to-HIGH RL = 75 Ω, CL = 5 pF, 1.0 1.2 1.3

tPHLD Differential Output Propagation Delay VCC = 3.3V, TA = 25°C0.71.6

HIGH-to-LOW See Figure 4 and Figure 5 1.0 1.2 1.3

tTLHD Differential Output Rise Time (20% to 80%) 290 580 ps

tTHLD Differential Output Fall Time (80% to 20%) 290 580 ps

tPLH Selection Propagation Delay 0.6 1.5 ns

LOW-to-HIGH (SELn to OUTn)R

L = 75 Ω, CL = 5 pF, 0.9 1.1 1.2

tPHL Selection Propagation Delay VCC = 3.3V, TA = 25°C0.61.5

HIGH-to-LOW (SELn to OUTn) See Figure 6 and Figure 7 0.9 1.1 1.2

tZHD Differential Output Enable Time 3.5 ns

from Z-to-HIGH

tZLD Differential Output Enable Time 3.5 ns

from Z-to-LOW RL = 75Ω, CL = 5 pF

tHZD Differential Output Disable Time See Figure 8 and Figure 9 3.5 ns

from HIGH-to-Z

tLZD Differential Output Disable Time 3.5 ns

from LOW-to-Z

tSET Input (INn+/INn−) Setup Time to SELnSee Figure 10 0.5 0.3 ns

tHOLD Input (INn+/INn−) Hold Time to SELnSee Figure 10 0.5 0.3 ns

tJIT Output Peak-to-Peak Jitter 223 −1 PRBS Sequence at 800 Mbps 190 ps

50% Duty Cycle at 800 Mbps 20 35 ps

fTOG Maximum Toggle Frequency RL = 75 Ω, CL = 5 pF, See Figure 4 800 900 Mbps

tSKEW Within Device Channel-to-Channel Skew 35 80 ps

Pulse Skew |tPLHD -tPHLD|0 225 ps

Part-to-Part Skew (Note 5) 100 500 ps

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Required Specifications

1. When the true and complement LVDS outputs (having

a 75Ω connected between outputs) are connected to

3.75 kΩ resistors and the common point of those 3.75

kΩ resistors are connected to a voltage source that

sweeps from 0 to 2.4V, the DC VOD and ∆VOD are still

maintained (see Figure 1).

2. When the true and complement LVDS outputs (having

a 5 pF capacitor attached between outputs) are con-

nected with 37.5Ω resistors each to common point,

then the common point does not vary by more than 150

mV under all process, temperature and voltage condi-

tions when the outputs switch either from LOW-to-

HIGH or from HIGH-to-LOW (see Figure 2).

3. Pull-down resistors are required on Enable (EN0 and

EN1) and select (SEL0 and SEL1) inputs.

4. Fail safe protection on the outputs that draw less than

20 µA of current (worst case) on the LVDS inputs. In

this condition, if the input is in fail safe selected to

OUT0+/OUT0− (say) and the outputs are Enabled then

OUT0+ = HIGH and OUT0− = LOW. This prevents noise

from being amplified when the connection is broken.

5. In the disabled state the outputs can go beyond VCC

but there should be no appreciable leakage (see IOZD

and IOFF specifications)

FIGURE 1. Common Mode Supply Test Circuit

FIGURE 2. Dynamic VOS Test Circuit and Waveforms

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Required Specifications (Continued)

FIGURE 3. LVDS Driver DC Test Circuit

Note A: All input pulses have frequency = 50 MHz, tR or tF = 500 ps

Note B: CL includes all probe and jig capacitances

FIGURE 4. LVDS Input to LVDS Driver Propagation

Delay and Transition Time Circuit

FIGURE 5. LVDS Input to LVDS Output AC Waveforms FIGURE 6. LVTTL Input to LVDS Driver Propagation

Delay and Transition Time Test Circuit

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Required Specifications (Continued)

FIGURE 7. LVTTL Input to LVDS Output AC Waveforms

Note A: All input pulses have frequency = 10MHz, tR or tF < = 1 ns.

Note B: CL includes all probe and jig capacitances.

FIGURE 8. Differential Driver Enable

and Disable Test Circuits

FIGURE 9. Enable and Disable AC Waveforms

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Required Specifications (Continued)

FIGURE 10. Set-up and Hold Time Specification

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems