FDD8876, FDU8876 Datasheet by onsemi

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FAI RCHII—Dw TJ 5T5 BJA

FDD8876 / FDU8876

N-Channel PowerTrench® MOSFET

30V, 73A, 8.2mΩ

General Description

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using

either synchronous or conventional switching PWM

controllers. It has been optimized for low gate charge, low

rDS(ON) and fast switching speed.

Applications

• DC/DC converters

Features

•r

DS(ON) = 8.2mΩ, VGS = 10V, ID = 35A

•r

DS(ON) = 10mΩ, VGS = 4.5V, ID = 35A

• High performance trench technology for extremely low

rDS(ON)

• Low gate charge

• High power and current handling capability

MOSFET Maximum Ratings TC = 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter Ratings Units

VDSS Drain to Source Voltage 30 V

VGS Gate to Source Voltage ±20 V

Drain Current

73 A

Continuous (TC = 25oC, VGS = 10V) (Note 1)

Continuous (TC = 25oC, VGS = 4.5V) (Note 1) 66 A

Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 52oC/W) 15 A

Pulsed Figure 4 A

EAS Single Pulse Avalanche Energy (Note 2) 95 mJ

PDPower dissipation 70 W

Derate above 25oC0.47W/

TJ, TSTG Operating and Storage Temperature -55 to 175 oC

RθJC Thermal Resistance Junction to Case TO-252, TO-251 2.14 oC/W

RθJA Thermal Resistance Junction to Ambient TO-252, TO-251 100 oC/W

RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W

GDS

I-PAK

(TO-251AA)

TO-252

D-PAK

(TO-252)

• RoHS Compliant

March 2015

FDD8876 / FDU8876

Package Marking and Ordering Information

Electrical Characteristics TC = 25°C unless otherwise noted

Off Characteristics

On Characteristics

Dynamic Characteristics

Switching Characteristics (VGS = 10V)

Drain-Source Diode Characteristics

Notes:

1: Package current limitation is 35A.

2: Starting TJ = 25°C, L = 0.24mH, IAS = 28A, VDD = 27V, VGS = 10V.

Device Marking Device Package Reel Size Tape Width Quantity

FDD8876 FDD8876 TO-252AA 13”16mm 2500 units

FDU8876 FDU8876 TO-251AA Tube N/A 75 units

Symbol Parameter Test Conditions Min Typ Max Units

BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

IDSS Zero Gate Voltage Drain Current VDS = 24V - - 1 µA

VGS = 0V TC = 150oC - - 250

IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

rDS(ON) Drain to Source On Resistance

ID = 35A, VGS = 10V - 0.0066 0.0082

Ω

ID = 35A, VGS = 4.5V - 0.008 0.010

ID = 35A, VGS = 10V,

TJ = 175oC- 0.011 0.013

CISS Input Capacitance VDS = 15V, VGS = 0V,

f = 1MHz

- 1700 - pF

COSS Output Capacitance - 330 - pF

CRSS Reverse Transfer Capacitance - 200 - pF

RGGate Resistance VGS = 0.5V, f = 1MHz - 2.2 - Ω

Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V

VDD = 15V

ID = 35A

Ig = 1.0mA

-3447nC

Qg(5) Total Gate Charge at 5V VGS = 0V to 5V - 18 26 nC

Qg(TH) Threshold Gate Charge VGS = 0V to 1V - 1.4 1.9 nC

Qgs Gate to Source Gate Charge - 4.2 - nC

Qgs2 Gate Charge Threshold to Plateau - 2.8 - nC

Qgd Gate to Drain “Miller” Charge - 8.0 - nC

tON Turn-On Time

VDD = 15V, ID = 35A

VGS = 10V, RGS = 10Ω

- - 149 ns

td(ON) Turn-On Delay Time - 8 - ns

trRise Time - 91 - ns

td(OFF) Turn-Off Delay Time - 44 - ns

tfFall Time - 37 - ns

tOFF Turn-Off Time - - 122 ns

VSD Source to Drain Diode Voltage ISD = 35A - - 1.25 V

ISD = 15A - - 1.0 V

trr Reverse Recovery Time ISD = 35A, dISD/dt = 100A/µs- -26ns

QRR Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs- -12nC

FDD8876 / FDU8876

Typical Characteristics TC = 25°C unless otherwise noted

Figure 1. Normalized Power Dissipation vs Case

Temperature Figure 2. Maximum Continuous Drain Current vs

Case Temperature

Figure 3. Normalized Maximum Transient Thermal Impedance

Figure 4. Peak Current Capability

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0 25 50 75 100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150 0

25 50 75 100 125 150 175

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

CURRENT LIMITED

BY PACKAGE

VGS = 4.5V

VGS = 10V

0.1

10-5 10-4 10-3 10-2 10-1 100101

0.01

t, RECTANGULAR PULSE DURATION (s)

ZθJC, NORMALIZED

THERMAL IMPEDANCE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

0.5

0.2

0.1

0.05

0.01

0.02

DUTY CYCLE - DESCENDING ORDER

SINGLE PULSE

100

1000

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

10-5 10-4 10-3 10-2 10-1 100101

TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 4.5V

FDD8876 / FDU8876

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

Figure 9. Drain to Source On Resistance vs Gate

Voltage and Drain Current Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

Typical Characteristics TC = 25°C unless otherwise noted

0.1

100

1000

110

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

TJ = MAX RATED

TC = 25oC

SINGLE PULSE

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

10µs

1ms

100µs

10ms

100

0.01 0.1 1

500

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

STARTING TJ = 150oC

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

100

1.5 2.0 2.5 3.0 3.5 4.0

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

TJ = 175oC

TJ = 25oC

TJ = -55oC

100

0 0.2 0.4 0.6 0.8 1.0

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V VGS = 4V

VGS = 3V

VGS = 5V

246810

ID = 1A

VGS, GATE TO SOURCE VOLTAGE (V)

ID = 35A

rDS(ON), DRAIN TO SOURCE

ON RESISTANCE (mΩ)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0.6

0.8

1.0

1.2

1.4

1.6

-80 -40 0 40 80 120 160 200

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

VGS = 10V, ID = 35A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

FDD8876 / FDU8876

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

Figure 13. Capacitance vs Drain to Source

Voltage Figure 14. Gate Charge Waveforms for Constant

Gate Current

Typical Characteristics TC = 25°C unless otherwise noted

0.4

0.6

0.8

1.0

1.2

-80 -40 0 40 80 120 160 200

VGS = VDS, ID = 250µA

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VOLTAGE

0.90

0.95

1.00

1.05

1.10

-80 -40 0 40 80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

BREAKDOWN VOLTAGE

100

1000

0.1 1 10

5000

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

CISS = CGS + CGD

COSS ≅ CDS + CGD

CRSS = CGD

0 5 10 15 20 25 30

VGS, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15V

ID = 35A

ID = 5A

WAVEFORMS IN

DESCENDING ORDER:

FDD8876 / FDU8876

Test Circuits and Waveforms

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 1V

Qgs2

Qg(TOT)

VGS = 10V

VDS VGS

Ig(REF)

Qgs Qgd

Qg(5)

VGS = 5V

VGS

RGS

DUT

VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

FDD8876 / FDU8876

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PDM, in an

application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the TO-252

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of PDM is

complex and influenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and equation 3 is for area in centimeters

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

(EQ. 1)

PDM

TJM TA

–()

RθJA

-----------------------------=

Area in Inches Squared

(EQ. 2)

RθJA 33.32 23.84

0.268 Area+()

-------------------------------------+

(EQ. 3)

RθJA 33.32 154

1.73 Area+()

----------------------------------+

Area in Centimeters Squared

100

125

0.01 0.1 1 10

Figure 21. Thermal Resistance vs Mounting

Pad Area

RθJA = 33.32+ 23.84/(0.268+Area) EQ.2

RθJA (oC/W)

AREA, TOP COPPER AREA in2 (cm2)

RθJA = 33.32+ 154/(1.73+Area) EQ.3

(0.645) (6.45) (64.5)(0.0645)

FDD8876 / FDU8876

PSPICE Electrical Model

.SUBCKT FDD8876 2 1 3 ; rev January 2004

Ca 12 8 1.9e-9

Cb 15 14 1.6e-9

Cin 6 8 1.55e-9

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 33.15

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 4.7e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 1.7e-9

RLgate 1 9 47

RLdrain 2 5 10

RLsource 3 7 17

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 2.9e-3

Rgate 9 20 2.2

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 2.7e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*300),10))}

.MODEL DbodyMOD D (IS=3E-12 IKF=10 N=1.01 RS=3.4e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=6.3e-10 M=0.57 TT=1e-17 XTI=2)

.MODEL DbreakMOD D (RS=1 TRS1=1e-3 TRS2=-8.9e-6)

.MODEL DplcapMOD D (CJO=6.1e-10 IS=1e-30 N=10 M=0.41)

.MODEL MmedMOD NMOS (VTO=1.95 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2 T_ABS=25)

.MODEL MstroMOD NMOS (VTO=2.45 KP=250 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)

.MODEL MweakMOD NMOS (VTO=1.65 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1 T_ABS=25)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)

.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)

.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)

.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)

.MODEL RvthresMOD RES (TC1=-1.7e-3 TC2=-8.2e-6)

.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

FDD8876 / FDU8876

SABER Electrical Model

rev January 2004

template FDD8876 n2,n1,n3 =m_temp

electrical n2,n1,n3

number m_temp=25

{

var i iscl

dp..model dbodymod = (isl=3e-12,ikf=10,nl=1.01,rs=3.4e-3,trs1=8e-4,trs2=2e-7,cjo=6.3e-10,m=0.57,tt=1e-17,xti=2)

dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-8.9e-6)

dp..model dplcapmod = (cjo=6.1e-10,isl=10e-30,nl=10,m=0.41)

m..model mmedmod = (type=_n,vto=1.95,kp=10,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=2.45,kp=250,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=1.65,kp=0.05,is=1e-30, tox=1,rs=0.1)

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5)

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4)

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2)

c.ca n12 n8 = 1.9e-9

c.cb n15 n14 = 1.6e-9

c.cin n6 n8 = 1.55e-9

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 33.15

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lgate n1 n9 = 4.7e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 1.7e-9

res.rlgate n1 n9 = 47

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 17

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7

res.rdrain n50 n16 = 2.9e-3, tc1=1e-4,tc2=8e-6

res.rgate n9 n20 = 2.2

res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 2.7e-3, tc1=7.5e-3,tc2=1e-6

res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8.2e-6

res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/300))** 10))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK

DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

FDD8876 / FDU8876

PSPICE Thermal Model

REV 23 January 2004

FDD8876T

CTHERM1 TH 6 7e-4

CTHERM2 6 5 9e-4

CTHERM3 5 4 2e-3

CTHERM4 4 3 2.5e-3

CTHERM5 3 2 6e-3

CTHERM6 2 TL 1.1e-2

RTHERM1 TH 6 7.0e-2

RTHERM2 6 5 1.1e-1

RTHERM3 5 4 2.2e-1

RTHERM4 4 3 3.2e-1

RTHERM5 3 2 4.9e-1

RTHERM6 2 TL 5e-1

SABER Thermal Model

SABER thermal model FDD8876T

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 =7e-4

ctherm.ctherm2 6 5 =9e-4

ctherm.ctherm3 5 4 =2e-3

ctherm.ctherm4 4 3 =2.5e-3

ctherm.ctherm5 3 2 =6e-3

ctherm.ctherm6 2 tl =1.1e-2

rtherm.rtherm1 th 6 =7.0e-2

rtherm.rtherm2 6 5 =1.1e-1

rtherm.rtherm3 5 4 =2.2e-1

rtherm.rtherm4 4 3 =3.2e-1

rtherm.rtherm5 3 2 =4.9e-1

rtherm.rtherm6 2 tl =5e-1

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

6 73 6.35 546 ‘ 521 F %2 MAX DIODE FRODucTS VERSION L, L I_ g 2 I 0.25 MA>

FAIRGHILD. R“ svs1EM , Amuse GENERAL‘ +_ rig MmmnMax Xscns WEBSITE AT H‘I'I'P4 www FAWRCH‘LDSEM‘ COM

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TinyLogic

TINYOPTO

TinyPower

TinyPWM

TinyWire

TranSiC

TriFault Detect

TRUECURRENT

μSerDes

UHC

Ultra FRFET

UniFET

VCX

VisualMax

VoltagePlus

XS™

Xsens™

仙童

™

* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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Unless otherwise specified in this data sheet, this product is a standard commercial product and is not intended for use in applications that require extraordinary

levels of quality and reliability. This product may not be used in the following applications, unless specifically approved in writing by a Fairchild officer: (1) automotive

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ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,

under Terms of Use

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their

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proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild

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and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise.

Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global

problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change

in any manner without notice.

Preliminary First Production

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild

Semiconductor reserves the right to make changes at any time without notice to improve design.

No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make

changes at any time without notice to improve the design.

Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.

The datasheet is for reference information only.

Rev. I75

FDD8876, FDU8876 Datasheet by onsemi

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