The is an integral DS3/E3 framer designed to support the transmission formats defined by ANSI T1.107a-1989, T1.404, and ITU-T G.751 standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing overhead. The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751 E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be enabled to reduce jitter on the incoming data. Transmit and receive data is available to the host in either serial or parallel byte and nibble formats. Access is provided to the terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations (LCVs), parity errors, and Far End Block Errors (FEBEs). Two operational modes are available: microprocessor and stand-alone monitor control modes. The microprocessor control mode monitors all status conditions and provides configuration control. The stand-alone monitor mode allows the CN8330 to operate as a monitor providing status and alarm information on external pins.

Supports DS3/E3 framing modes Includes high-speed HDLC controller (52 MHz) Framing recovery for M13, C-bit parity, Syntran, and G.751 E3 signals Serial or parallel (octet or nibble) interface modes Average reframe time of less than 1 ms for DS3 and less than 250 �s for E3 Supports the LAPD terminal data link and FEAC channel as defined T1.107a-1989 68-pin PLCC or 80-pin MQFP surface-mount package Operates from a single +5 VDC �5% power supply Low-power CMOS technology

Digital PCM switches Digital Cross-Connect Systems Channel Service Units (CSUs) Channel extenders ATM Switches/Concentrators PBXs Switched Multimegabit Digital Service (SMDS) Equipment Test equipment Routers (including HSSI ports)

Bypass RXPOS RXNEG DS3CKI TXCKI U X Unipolar Conversion FIFO Framing Recovery RXMSY CBITO RXCCK RXDAT FIFO Enable Source Loopback Overhead/ Data Link Processing PPDL Receiver TXPOS TXNEG TCLKO U X Bipolar Encoder RXCLK

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2.1 Overview. Brief Block Description. Clock Interface and Initialization. 2.1.2.1 Initialization. Microprocessor Interface. 2.1.3.1 Using with Specific Microcontrollers. 2.1.3.2 Microprocessor Interrupts. 2.1.3.3 Address Map.

Line Interfaces. 2.2.1 2.2.2 Transmitter Line Interface. 2-5 Receiver Line Interface. 2-6 Input and Synchronization. 2-7 DS3 Mode. 2-7 E3 Mode. 2-9 Framing Bit Generation. 2-10 Alarm Signal Generation. 2-11 Terminal Data Link Transmitter. 2-12 2.3.6.1 Sending a Message. 2-13 2.3.6.2 Aborting a Message. 2-14 2.3.6.3 Transmitter Interrupts. 2-14 2.3.6.4 Transmitter Control Example. 2-15 TxFEAC Channel Transmission. 2-15 PPDL Transmitter. 2-16 PPDLONLY Mode. 2-20 Transmitter Outputs. 2-20 Test Equipment Specific Features. 2-21