ADSST-21065LCS-240 datasheet - High End, Multichannel, 32-bit Floating-point Audio

Details, datasheet, quote on part number: ADSST-21065LCS-240
PartADSST-21065LCS-240
CategoryAnalog & Mixed-Signal Processing => Amplifiers => Audio/Power Amplifiers
DescriptionHigh End, Multichannel, 32-bit Floating-point Audio Processor
CompanyST Microelectronics, Inc.
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Features, Applications

High End, Multichannel, 32-Bit Floating-Point Audio Processor SST-Melody -SHARC

FEATURES Super Harvard Architecture Computer (SHARC) 4 Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory, Integrated I/O Peripheral I 2S Support for 8 Simultaneous Receive and Transmit Channels 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory 2 External Port, DMA Channels and 8 Serial Port, DMA Channels Decodes Industry Standard Formats Using a 32-Bit Floating Point Implementation for Decoding Dolby� Digital AC-3, Dolby Digital EX Processing Dolby Pro Logic�, 96 kHz, Dolby Pro Logic II Dolby Headphone, Dolby 3/0 DTS� 5.1, DTS-ES�-Discreet 6.1, DTS Matrix and Matrix 3.0, DTS 96/24 DTS NEO:6 THX � Ultra, Select, 7.1, EX SRS � Labs Circle Surround II TM, Virtual Loudspeaker MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode PCM, PCM 96 kHz HDCD, MLP* Delay 7.1, 96 kHz Bass 7.1, 96 kHz, Bass/Treble 2 Channel ADI Surround: Club, Music, and Stadium AAC (LC), AAC (LC) 2 Channel, AAC MP WaveSurround 5.1 Channel to Headphone, Stereo to Headphone, Channel to Loudspeaker, Stereo to Loudspeaker Downsampling 96 kHz to 48 kHz (2-Channel) 3-Band Equalizer, 2-Channel Encoders: AC-3 2-Channel Consumer Encoder Single Chip DSP-Based Implementation of Digital Audio Algorithms I2S Compatible Ports Interface to External SDRAM

Easy Interfaces to Audio Codecs 96 kHz Processing Supports Customer Specific Post Processing Automatic Stream Detection and Code Loading Easy to Use Software Architecture Optimized Library of Routines Host Communication Using 16-Bit Parallel Port or SPI Port Highly Flexible Serial Ports SRAM Interface for More Delay Supports IEC60958 For Bit Streams 8-Channel Output Using TDM Codecs APPLICATIONS Home Theater AVR Systems Automotive Audio Receivers Video Game Consoles DVD Players Cable and Satellite Set-Top Boxes Multimedia Audio/Video Gateways

Melody and SHARC are registered trademarks of Analog Devices, Inc. DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater Systems, Inc. Dolby and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. SRS is a registered trademark and Circle Surround is a trademark of SRS Labs. THX is a registered trademark of the THX, Ltd. *MLP is implemented, not certified.

The SST-Melody-SHARC family of powerful 32-bit Audio Processors from Analog Devices provides flexible solutions and delivers a host of features across high end and high fidelity audio systems to the AV receiver and DVD markets. It includes multichannel audio decoders, encoders, and post processors for digital audio designs using DSP chipsets in home theater systems and automotive audio receivers. (continued on page 11)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 � Analog Devices, Inc., 2002

Parameter VDD TCASE VIH VIL1 VIL2 Test Conditions Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = max Low Level Input Voltage2 @ VDD = min Low Level Input Voltage3 @ VDD = min Min C Grade Max 3.60 +100 VDD K Grade Min Max VDD Unit �C V

NOTES 1 See Environmental Conditions section for information on thermal specifications. 2 Applies to input and bidirectional pins: DATA31�0, ADDR23�0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2�0, FLAG11�0, HBG, CS, BR2�1, ID2�0, RPBA, CPA, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, RCLK0, RCLK1, RESET , TRST, PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE. 3 Applies to input pin CLKIN.

Parameter VOH VOL IIH IIL IILP IOZH IOZL IOZLS IOZLA IOZLAR IOZLC CIN High Level Output Voltage Low Level Output Voltage1 High Level Input Current3 Low Level Input Current3 Low Level Input Current4 Three-State Leakage 7, 8 Three-State Leakage Current5 Three-State Leakage Current6 Three-State Leakage Current9 Three-State Leakage Current8 Three-State Leakage Current7 Input Capacitance10, 11

Test Conditions @ VDD = min, IOH mA @ VDD = min, IOL mA2 @ VDD = max, VIN = VDD max @ VDD = max, VIN VDD = max, VIN VDD = max, VIN = VDD max @ VDD = max, VIN VDD = max, VIN VDD = max, VIN V @ VDD = max, VIN VDD = max, VIN 0 V fIN = 1 MHz, TCASE = 25�C, VIN 2.5 V

NOTES 1 Applies to output and bidirectional pins: DATA31�0, ADDR 23�0, MS3�0, RD, WR, SW, ACK, FLAG11�0, HBG, REDY, DMAG2, BR2�1, CPA, DT0B, DT1B, XTAL, BMS , TDO, EMU , BMSTR, PWM_EVENT0, PWM_EVENT1, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10. 2 See Output Drive Current section for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2�0, HBR, CS, DMAR2, ID1�0, BSEL, CLKIN, RESET , TCK (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when = 01 and another SST-Melody-SHARC is not requesting bus mastership). 4 Applies to input pins with internal pull-ups: DR0B, DR1B, TRST, TMS, TDI. 5 Applies to three-statable pins: DATA31�0, ADDR 23�0, MS3�0, RD, WR, SW, ACK, FLAG11�0, REDY, HBG, DMAG1, DMAG2, BMS , TDO, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when = 01 and another SST-Melody-SHARC is not requesting bus mastership). 6 Applies to three-statable pins with internal pull-ups: RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. 9 Applies to ACK pin when keeper latch enabled. 10 Guaranteed but not tested. 11 Applies to all signal pins. Specifications subject to change without notice.

Supply Voltage. +4.6 V Input Voltage. V to VDD 0.5 V Output Voltage Swing. V to VDD 0.5 V Load Capacitance. 200 pF Junction Temperature Under Bias. 130�C Storage Temperature Range. to +150�C Lead Temperature (5 seconds). 280�C

*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SST-Melody-SHARC features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.


 

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