881E36A datasheet - Synchronous Burst SRAMs, 8Meg, 512K X 18,2.5 V And 3.3 V

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Details, datasheet, quote on part number: 881E36A

Part	881E36A
Category	Memory => SRAM => 8 Mb
Title	Burst SRAM
Description	Synchronous Burst SRAMs, 8Meg, 512K X 18,2.5 V And 3.3 V
Company	GSI Technology
Datasheet	Download 881E36A Datasheet
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Features, Applications

Preliminary GS881E18/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features

FT pin for user-configurable flow through or pipeline operation Dual Cycle Deselect (DCD) operation IEEE 1149.1 JTAG-compatible Boundary Scan V +10%/�10% core power supply 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 100-lead TQFP package Pipeline 2.5 V Flow Through 2.5 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) Unit ns mA

be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.

The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.

The is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Applications

The a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

The GS881E18/36AT operates 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.

Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positiveedge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can Rev: Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8662DT10BD-450 : 8M X 8 QDR SRAM, 0.45 ns, PBGA165 Specifications: Memory Category: SRAM Chip ; Density: 67109 kbits ; Number of Words: 8000 k ; Bits per Word: 8 bits ; Package Type: 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 ; Pins: 165 ; Supply Voltage: 1.8V ; Access Time: 0.4500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)

GS8662Q19BD-357 : 8M X 8 DDR SRAM, 0.45 ns, PBGA165 Specifications: Memory Category: SRAM Chip ; Density: 67109 kbits ; Number of Words: 8000 k ; Bits per Word: 8 bits ; Package Type: 13 X 15 MM, 1 MM PITCH, FPBGA-165 ; Pins: 165 ; Supply Voltage: 1.8V ; Access Time: 0.4500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)

GS880V37BGT-275T : 256K X 32 CACHE SRAM, 7.5 ns, PQFP100 Specifications: Memory Category: SRAM Chip ; Density: 8389 kbits ; Number of Words: 256 k ; Bits per Word: 32 bits ; Package Type: TQFP, LEAD FREE, TQFP-100 ; Pins: 100 ; Supply Voltage: 1.8V ; Access Time: 7.5 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)

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