Details, datasheet, quote on part number: 881Z18A
| Part | 881Z18A |
| Category | Memory => SRAM => Sync. SRAM => 8 Mb |
| Description | Synchronous NBT SRAMs, 8Meg, 512K X 18,2.5 V And 3.3 V |
| Company | GSI Technology |
| Datasheet | Download 881Z18A Datasheet |
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| Features, Applications |
Preliminary GS881Z18/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features User-configurable Pipeline and Flow Through mode NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs IEEE 1149.1 JTAG-compatible Boundary Scan On-chip write parity checking; even or odd selectable V +10%/�10% core power supply 3.3 V I/O supply LBO pin for Linear or Interleave Burst mode Pin-compatible with 2M, 4M, and 8M devices Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion ZZ pin for automatic power-down JEDEC-standard 100-lead TQFP package Pipeline 2.5 V Flow Through 2.5 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) Unit ns mA The a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS881Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS881Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package. Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write CyclesSpecifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. |
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