ADCLK854
1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
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Features
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The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.
The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.
This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Low jitter clock distribution
- Clock and data signal restoration
- Level translation
- Wireless communications
- Wired communications
- Medical and industrial imaging
- ATE and high performance instrumentation
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Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
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ADCLK854
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217 kB
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Documentation
Product Selection Guide 1
Technical Articles 3
Tutorial 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADCLK854BCPZ |
48 ld LFCSP (7x7x.85mm w/2.8mm Pad)
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| ADCLK854BCPZ-REEL7 |
48 ld LFCSP (7x7x.85mm w/2.8mm Pad)
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- ADCLK854BCPZ
- Pin/Package Drawing
- 48 ld LFCSP (7x7x.85mm w/2.8mm Pad)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
-
SamacSys
- ADCLK854BCPZ-REEL7
- Pin/Package Drawing
- 48 ld LFCSP (7x7x.85mm w/2.8mm Pad)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
Filter by Model
Part Models
Product Lifecycle
PCN
Feb 1, 2024
- 24_0009
Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
May 12, 2017
- 16_0077
Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Feb 1, 2024
- 24_0009
Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
Jun 9, 2021
- 20_0126
Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
May 12, 2017
- 16_0077
Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.
ADCLK854BCPZ
PRODUCTION
ADCLK854BCPZ-REEL7
PRODUCTION
Software & Part Ecosystem
Evaluation Kits 1
EVAL-ADCLK854
ADCLK854 Evaluation Board
Product Detail
The ADCLK854 data sheet contains full technical details about the specifications and operation of this device and should be consulted when using the evaluation board.
The ADCLK854 is a high performance clock fanout buffer. The evaluation board is fabricated using a high quality Rogers® dielectric material. Transmission line paths are kept as close to 100 Ω differentially as possible.
Resources
Evaluation Kits1
Tools & Simulations 2
IBIS Model 2
IBIS Model
ADIsimCLK Design and Evaluation Software
