83C453 Datasheet, PDF(8/26 Page) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
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83C453 Datasheet, PDF (8/26 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
83C453/87C453
MSB
LSB
—
POB PIB
PS
PT1 PX1 PT0 PX0
BIT
SYMBOL FUNCTION
IP.7
—
Reserved.
IP.6
POB
Defines the Output Buffer Full interrupt (IOB) priority level. POB=1 programs it to the higher priority level.
IP.5
PIB
Defines the Input Buffer Full interrupt (IIB) priority level. PIB=1 programs it to the higher priority level.
IP.4
PS
Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level.
IP.3
PT1
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.
IP.2
PX1
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.
IP.1
PT0
Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher priority level.
IP.0
PX0
Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
SU00564
Figure 3. 8XC453 Interrupt Priority (IP) Register
7
6
5
4
3
2
1
0
PCON (87H) SMOD1 SMOD2 —
POF GF1 GF0
PD
IDL
BIT
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
SYMBOL
SMOD1
SMOD0
—
POF
GF1
GF0
PD
IDL
FUNCTION
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port
is used in modes 1, 2, or 3.
If set to 1, SCON.7 will be the Framing Error bit (FE). If PCON.6 is cleared, SCON.7 will be SM0.
Reserved.
Power Off Flag is set during power on of VCC. If then cleared by software, it can be used to determine
if a warm start has occurred.
General-purpose flag bit.
General-purpose flag bit.
Power-Down bit. Setting this bit activates power-down mode. It can only be set if input EW is high.
Idle mode bit. Setting this bit activates the idle mode.
If logic 1s are written to PD and IDL at the same time, PD takes precedence.
Figure 4. Power Control Register (PCON)
SU00565
Table 2. Interrupt Table
POLLING
REQUEST
PRIORITY SOURCE BITS/FLAG
1
INTO
IE0
2
Timer0
TF0
3
INT1
IE1
4
Timer1
TF1
5
Port 6
OBF
6
Serial I/O RI,TI
7
Port 6
IBF
VECTOR
ADDRESS
03H highest priority
0BH
13H
1BH
33H
23H
2BH lowest priority
1998 Apr 23
8
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