Details, datasheet, quote on part number: 82801EB
| Part | 82801EB |
| Category | Interface and Interconnect => Chipsets |
| Description | Intel 82801EB I/o Controller Hub 5 (ICH5) And Intel 82801ER I/o Controller Hub 5 R (ICH5R) |
| Company | Intel Corporation |
| Datasheet | Download 82801EB Datasheet |
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| Features, Applications |
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL� PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel� 82801EB I/O Controller Hub (ICH5) / Intel� 82801ER I/O Controller Hub R (ICH5R) chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright � 2002�2003, Intel Corporation New: Supports PCI Revision 2.3 Specification at 33 MHz 6 available PCI REQ/GNT pairs One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller) Support for 44-bit addressing on PCI using DAC protocol New: Integrated ASF Management Controller WfM 2.0 and IEEE 802.3 Compliant LAN Connect Interface (LCI) 10/100 Mbit/sec Ethernet Support Independent DMA operation on two ports. Data transfer rates to 1.5 Gb/s (150 MB/s). RAID Level 0 Support (ICH5R Only) Supports "Native Mode" Register and Interrupts Independent timing to 4 drives Ultra ATA/100/66/33, BMIDE and PIO modes Tri-state modes to enable swap bay New: Includes 4 UHCI Host Controllers, increasing the number of external ports to eight Includes 1 EHCI Host Controller that supports all eight ports Includes 1 USB 2.0 high-speed debug port Supports wake-up from sleeping states S1�S5 Supports legacy Keyboard/Mouse software Support for `97 2.3 codecs. Independent bus master logic for 8 channels (PCM In/Out, PCM2 In, Mic 1 Input, Mic 2 Input, Modem In/Out, S/PDIF Out) Support for up to six channels of PCM audio output (full AC3 decode) Supports wake-up events Supports to 8 PCI interrupt pins Supports PCI 2.3 Message Signaled Interrupts Two cascaded 82C59 with 15 interrupts Integrated I/O APIC capability with 24 interrupts Supports Front Side Bus interrupt delivery Advanced operating system interrupt scheduling 5V tolerant buffers on IDE, PCI, USB Overcurrent and Legacy signals System timer, Refresh request, Speaker tone output New: ACPI 2.0 compliant ACPI-defined power states (C1, S3�S5) ACPI Power Management Timer PCI PME# support SMI# generation All registers readable/restorable for proper resume from 0 V suspend states Support for APM-based legacy power management for non-ACPI implementations Integrated Pull-up, Pull-down and Series Termination resistors on IDE, processor I/F Integrated Pull-down and Series resistors on USB I Flash BIOS I/F supports BIOS Memory size up toSupports two Master/DMA devices. Support for Security Devices connected to LPC. Two cascaded 8237 DMA controllers PCI DMA: Supports PC/PCI Includes two PC/PCI REQ#/GNT# pairs Supports LPC DMA Supports DMA Collection Buffer to provide TypeF DMA performance for all DMA channels 256-byte battery-backed CMOS RAM Integrated oscillator components Lower Power DC/DC Converter implementation Timers to generate SMI# and Reset upon detection of system hang Timers to detect improper processor reset Integrated processor frequency strap logic Supports ability to disable external devices New: Provides independent manageability bus through SMLink interface. Supports SMBus 2.0 Specification Host interface allows processor to communicate via SMBus Slave interface allows an internal or external Microcontroller to access system resources Compatible with most 2-Wire components that are also I2C compatible TTL, Open-Drain, Inversion The Intel� / ICH5R may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. |
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