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Intel 80C186EB Manual

16-bit high-integration embedded processors
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80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Integrated Feature Set
Y
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Direct Addressing Capability to 1 Mbyte
Y
Memory and 64 Kbyte I O
Speed Versions Available (5V)
Y
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
X
Full Static Operation
X
True CMOS Inputs and Outputs
Available in Extended Temperature
Y
Range (
Speed Versions Available (3V)
Y
Low-Power Operating Modes
Y
Supports 80C187 Numeric Coprocessor
Y
Interface (80C186EB PLCC Only)
Available In
Y
October 1995
INTEL CORPORATION 1995
40 C to
85 C)
b
a
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
8 MHz (80L186EB8 80L188EB8)
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
272433 –1
Order Number 272433-004

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Summary of Contents for Intel 80C186EB

  • Page 1 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make...

  • Page 2: Table Of Contents

    80C186EB 80C188EB and 80L186EB 80L188EB 16-Bit High-Integration Embedded Processors CONTENTS CONTENTS PAGE PAGE Recommended Connections INTRODUCTION DC SPECIFICATIONS CORE ARCHITECTURE versus Frequency and Voltage Bus Interface Unit PDTMR Pin Delay Calculation Clock Generator AC SPECIFICATIONS 80C186EC PERIPHERAL AC Characteristics 80C186EB25...
  • Page 3 80C186EB 80C188EB 80L186EB 80L188EB 272433 – 2 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB Block Diagram...

  • Page 4: Introduction

    ‘‘C’’ and ‘‘L’’ devices are identical Bus Interface Unit The 80C186EB is the first product in a new genera- The 80C186EB core incorporates a bus controller tion of low-power high-integration microprocessors that generates local bus control signals In addition...

  • Page 5: 80C186Ec Peripheral Architecture

    20 pF 2 pF Interrupt Control Unit Drive Level 1 mW max The 80C186EB can receive interrupts from a num- ber of sources both internal and external The inter- 80C186EB PERIPHERAL rupt control unit serves to merge these requests on ARCHITECTURE...
  • Page 6 80C186EB 80C188EB 80L186EB 80L188EB Function Function Function Function Offset Offset Offset Offset Reserved Timer2 Count GCS0 Start Reserved End Of Interrupt Timer2 Compare GCS0 Stop Reserved Poll Reserved GCS1 Start Reserved Poll Status Timer2 Control GCS1 Stop Reserved Interrupt Mask...

  • Page 7: Serial Communications Unit

    80C187 Numerics Coproc- I O Port Unit essor The I O Port Unit (IPU) on the 80C186EB supports two 8-bit channels of input output or input output ONCE Test Mode operation Port 1 is multiplexed with the chip select...

  • Page 8: Package Information

    (P) ground (G) input only (I) output only (O) or This section describes the pins pinouts and thermal input output (I O) Some pins have multiplexed characteristics for the 80C186EB in the Plastic functions (for example A19 S6) Additional symbols Leaded Chip Carrier (PLCC) package Shrink Quad...
  • Page 9 80C186EB 80C188EB 80L186EB 80L188EB Table 2 Pin Description Nomenclature Symbol Description Power Pin (Apply Voltage) Ground (Connect to V Input Only Pin Output Only Pin Input Output Pin S(E) Synchronous Edge Sensitive S(L) Synchronous Level Sensitive A(E) Asynchronous Edge Sensitive...
  • Page 10 TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active (TEST) (LOW) TEST is alternately known as BUSY when interfacing with an 80C187 numerics coprocessor (80C186EB only) AD15 0 S(L) H(Z)
  • Page 11 BHE and (RFSH) R(Z) A0 have the following logical encoding P(X) Encoding (for the 80C186EB 80L186EB only) Word Transfer Even Byte Transfer Odd Byte Transfer Refresh Operation On the 80C188EB 80L188EB RFSH is asserted low to indicate a...
  • Page 12 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions (Continued) Input Output Description Name Type Type States DT R H(Z) Data Transmit Receive output controls the direction of a bi-directional buffer in a buffered system DT R is only R(Z) available for the PLCC package...
  • Page 13 80C186EB 80C188EB 80L186EB 80L188EB Table 3 Pin Descriptions (Continued) Input Output Description Name Type Type States T0OUT H(Q) Timer OUTput pins can be programmed to provide a single clock or continuous waveform generation T1OUT R(1) depending on the timer mode selected...

  • Page 14: 80C186Eb Pinout

    80C186EB 80C188EB 80L186EB 80L188EB Tables 6 and 7 list the 80C186EB 80C188EB pin 80C186EB PINOUT names with package location for the 80-pin Quad Flat Pack (QFP) component Figure 6 depicts the Tables 4 and 5 list the 80C186EB 80C188EB pin...
  • Page 15 80C186EB 80C188EB 80L186EB 80L188EB Table 5 PLCC Package Locations with Pin Name Location Name Location Name Location Name Location Name CLKOUT ERROR (N C ) P1 4 GCS4 T0OUT P1 3 GCS3 T0IN AD9 (A9) P1 2 GCS2 T1OUT P1 1 GCS1...
  • Page 16 80C186EB 80C188EB 80L186EB 80L188EB 272433 – 5 NOTE This is the FPO number location (indicated by X’s) Pin names in parentheses apply to the 80C188EB 80L188EB Figure 4 84-Pin Plastic Leaded Chip Carrier Pinout Diagram...
  • Page 17 80C186EB 80C188EB 80L186EB 80L188EB Table 6 QFP Pin Name with Package Location Address Data Bus Bus Control Processor Control Name Location Name Location Name Location Name Location RESIN BHE (RFSH) RESOUT CLKIN P1 0 GCS0 OSCOUT P1 1 GCS1 CLKOUT...
  • Page 18 80C186EB 80C188EB 80L186EB 80L188EB Table 7 QFP Package Location with Pin Names Location Name Location Name Location Name Location Name CTS0 TXD0 AD12 (A12) INT0 RXD0 INT1 P2 5 BCLK0 AD13 (A13) HLDA INT2 INTA0 P2 3 SINT1 HOLD INT3 INTA1...
  • Page 19 80C186EB 80C188EB 80L186EB 80L188EB 272433 – 6 NOTE This is the FPO number location (indicated by X’s) Pin names in parentheses apply to the 80C188EB 80L188EB Figure 5 Quad Flat Pack Pinout Diagram...
  • Page 20 80C186EB 80C188EB 80L186EB 80L188EB Table 8 SQFP Pin Functions with Location AD Bus Bus Control Processor Control RESIN (RFSH ) RESOUT CLKIN OSCOUT P1 0 GCS0 CLKOUT P1 1 GCS1 TEST BUSY P1 2 GCS2 P1 3 GCS3 READY INT0...
  • Page 21 80C186EB 80C188EB 80L186EB 80L188EB 272433 – 7 NOTE XXXXXXXXC indicates Intel FPO number Pin names in parentheses apply to the 80C188EB 80L188EB Figure 6 SQFP Package...

  • Page 22: Package Thermal Specifications

    PACKAGE THERMAL from i (thermal resistance from the case to ambi- SPECIFICATIONS ent) with the following equation The 80C186EB 80L186EB is specified for operation when T (the case temperature) is within the range 40 C to 100 C (PLCC package) or...

  • Page 23: Electrical Specifications

    80C186EB 80C188EB 80L186EB 80L188EB ELECTRICAL SPECIFICATIONS NOTICE This data sheet contains preliminary infor- mation on new products in production It is valid for the devices indicated in the revision history The Absolute Maximum Ratings specifications are subject to change without notice...

  • Page 24: Dc Specifications

    80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80C186EB 80C188EB) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 3 mA (Min) Output High Voltage 2 mA (MIn)
  • Page 25 80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80L186EB16) (operating temperature 0 C to 70 C) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 1 6 mA (Min) (Note 1)
  • Page 26 80C186EB 80C188EB 80L186EB 80L188EB DC SPECIFICATIONS (80L186EB13 80L188EB13 80L186EB8 80L188EB8) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 1 6 mA (Min) (Note 1) Output High Voltage...

  • Page 27: Icc Versus Frequency And Voltage

    Device operating frequency tive values Device current NOTE Measuring C on a device like the 80C186EB The above equation applies to delay times greater would be difficult Instead C is calculated using than 10 ms and will compute the TYPICAL capaci-...

  • Page 28: Ac Specifications

    80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80C186EB25 25 MHz Symbol Parameter Units Notes INPUT CLOCK CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period...

  • Page 29: Ac Characteristics 80C186Eb20

    80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80C186EB25 (Continued) 25 MHz Symbol Parameter Units Notes SYNCHRONOUS INPUTS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 CHIS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0...
  • Page 30 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 20 MHz 13 MHz Symbol Parameter Units Notes INPUT CLOCK CLKIN Frequency CLKIN Period 38 5 CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK...
  • Page 31 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 (Continued) 20 MHz 13 MHz Symbol Parameter Units Notes SYNCHRONOUS INPUTS TEST NMI INT4 0 BCLK1 0 T1 0IN CHIS READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN...

  • Page 32: Ac Characteristics 80L186Eb16

    80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80L186EB16 16 MHz Symbol Parameter Units Notes INPUT CLOCK CLKIN Frequency CLKIN Period 31 25 CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay...
  • Page 33 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80L186EB16 (Continued) 16 MHz Symbol Parameter Units Notes SYNCHRONOUS INPUTS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 CHIS TEST NMI INT4 0 T1 0IN BCLK1 0 READY CTS1 0...
  • Page 34 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80L186EB13 80L186EB8 13 MHz 8 MHz Symbol Parameter Units Notes INPUT CLOCK CLKIN Frequency CLKIN Period 38 5 62 5 CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time...
  • Page 35 80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS AC Characteristics 80L186EB13 80L186EB8 (Continued) 13 MHz 8 MHz Symbol Parameter Units Notes SYNCHRONOUS INPUTS TEST NMI INT4 0 CHIS BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 T1 0IN...

  • Page 36: Relative Timings

    80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS (Continued) Relative Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter Units Notes RELATIVE TIMINGS ALE Rising to ALE Falling LHLL Address Valid to ALE Falling AVLL Chip Selects Valid to ALE Falling PLLL...

  • Page 37: Serial Port Mode 0 Timings

    80C186EB 80C188EB 80L186EB 80L188EB AC SPECIFICATIONS (Continued) Serial Port Mode 0 Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter Unit Notes TXD Clock Period T (n XLXL TXD Clock Low to Clock High (n XLXH TXD Clock Low to Clock High (n...

  • Page 38: Ac Test Conditions

    80C186EB 80C188EB 80L186EB 80L188EB AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance 272433 – 8 50 pF for all signals...
  • Page 39 80C186EB 80C188EB 80L186EB 80L188EB 272433 –10 NOTE 20% V Float 80% V CC k Figure 9 Output Delay and Float Waveform 272433 –11 Figure 10 Input Setup and Hold...
  • Page 40 80C186EB 80C188EB 80L186EB 80L188EB 272433 –12 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 11 Relative Signal Waveform 272433 –13 Figure 12 Serial Port Mode 0 Waveform...

  • Page 41: Derating Curves

    80C186EB 80C188EB 80L186EB 80L188EB DERATING CURVES TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE 272433 –14 Figure 13 TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE 272433 –15 Figure 14...

  • Page 42: Reset

    80C186EB 80C188EB 80L186EB 80L188EB circuit) The RESIN pin is designed to operate cor- RESET rectly using an RC reset circuit but the designer must ensure that the ramp time for V is not so The processor will perform a reset operation any...
  • Page 43 80C186EB 80C188EB 80L186EB 80L188EB Figure 15 Cold Reset Waveforms...
  • Page 44 80C186EB 80C188EB 80L186EB 80L188EB Figure 16 Warm Reset Waveforms...

  • Page 45: Bus Cycle Waveforms

    80C186EB 80C188EB 80L186EB 80L188EB bus signals to CLKOUT These figures along with BUS CYCLE WAVEFORMS the information present in AC Specifications allow the user to determine all the critical timing analysis Figures 17 through 23 present the various bus cy-...
  • Page 46 80C186EB 80C188EB 80L186EB 80L188EB 272433 –19 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 18 Write Cycle Waveforms...
  • Page 47 80C186EB 80C188EB 80L186EB 80L188EB 272433 –20 NOTE The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the AD15 0 (AD7 0) bus will float while the A19 16 (A19 8) bus remains driven and all bus control signals are driven to their...
  • Page 48 80C186EB 80C188EB 80L186EB 80L188EB 272433 –21 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 20 Interrupt Acknowledge Cycle Waveform...
  • Page 49 80C186EB 80C188EB 80L186EB 80L188EB 272433 –22 NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 21 HOLD HLDA Waveforms...
  • Page 50 80C186EB 80C188EB 80L186EB 80L188EB 272433 –23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 22 Refresh during Hold Acknowledge...
  • Page 51 80C186EB 80C188EB 80L186EB 80L188EB 272433 –24 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 23 Ready Waveforms...

  • Page 52: Execution Timings

    The fol- With a 16-bit BIU the 80C186EB has sufficient bus lowing instruction timings represent the minimum performance to ensure that an adequate number of...

  • Page 53: Instruction Set Summary

    80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER Move Register to Register Memory 1 0 0 0 1 0 0 w mod reg r m 2 12 2 12 Register memory to register...
  • Page 54 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER (Continued) SEGMENT Segment Override 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0...
  • Page 55 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles ARITHMETIC (Continued) IMUL Integer multiply (signed) 1 1 1 1 0 1 1 w mod 1 0 1 r m Register-Byte 25–28 25–28 Register-Word 34–37...
  • Page 56 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles LOGIC (Continued) Exclusive or Reg memory and register to either 0 0 1 1 0 0 d w mod reg r m 3 10...
  • Page 57 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER (Continued) Return from CALL Within segment 1 1 0 0 0 0 1 1 Within seg adding immed to SP 1 1 0 0 0 0 1 0...
  • Page 58 80C186EB 80C188EB 80L186EB 80L188EB INSTRUCTION SET SUMMARY (Continued) 80C186EB 80C188EB Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL Clear carry 1 1 1 1 1 0 0 0 Complement carry 1 1 1 1 0 1 0 1 Set carry...

  • Page 59: Errata

    (i e it does not remain active until the S1STS An 80C186EB 80L186EB with a STEPID value of register is read) If SINT1 is to be connected to 0001H has the following known errata A device with any of the processor interrupt lines (INT0 –...

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