74ALVC16373 by onsemi Datasheet | DigiKey

74ALVC16373 Datasheet by onsemi

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© 2005 Fairchild Semiconductor Corporation DS500687 www.fairchildsemi.com
October 2001
Revised May 2005
74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
■1.1V to 3.6V VCC supply operation
■3.6V tolerant inputs and outputs
■tPD (In to On)
3.5 ns max for 3.0V to 3.6V VCC
3.9 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
■Power-off high impedance inputs and outputs
■Support live insertion and withdrawal (Note 1)
■Uses patented noise/EMI reduction circuitry
■Latchup conforms to JEDEC JED78
■ESD performance:
Human body model 2000V
Machine model 200V
■Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74ALVC16373GX
(Note 2) BGA54A
(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74ALVC16373MTD
(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
123456 JHGFEDCBA
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74ALVC16373
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial (HIGH or LOW, inputs may not float)
Z
High Impedance
O0 Previous O0 before HIGH-to-LOW of Latch Enable
Pin Names Description
OEnOutput Enable Input (Active LOW)
LEnLatch Enable Input
I0–I15 Inputs
O0–O15 Outputs
NC No Connect
123456
AO0NC OE1LE1NC I0
BO2O1NC NC I1I2
CO4O3VCC VCC I3I4
DO6O5GND GND I5I6
EO8O7GND GND I7I8
FO10 O9GND GND I9I10
GO12 O11 VCC VCC I11 I12
HO14 O13 NC NC I13 I14
JO15 NC OE2LE2NC I15
Inputs Outputs
LE1OE1I0–I7O0–O7
XHXZ
HLLL
HLHH
LLXO
0
Inputs Outputs
LE2OE2I8–I15 O8–O15
XHXZ
HLLL
HLHH
LLXO
0
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74ALVC16373
Functional Description
The 74ALVC16373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The
3-STATE outputs are controlled by the Output Enable
(OEn) input. When OEn is LOW the standard outputs are in
the 2-state mode. When OEn is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC16373
Absolute Maximum Ratings(Note 4) Recommended Operating
Conditions (Note 6)
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (VCC)0.5V to 4.6V
DC Input Voltage (VI)0.5V to 4.6V
Output Voltage (VO) (Note 5) 0.5V to VCC 0.5V
DC Input Diode Current (IIK)
VI 0V 50 mA
DC Output Diode Current (IOK)
VO 0V 50 mA
DC Output Source/Sink Current
(IOH/IOL)50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND) 100 mA
Storage Temperature Range (TSTG)65 C to 150 C
Power Supply
Operating 1.65V to 3.6V
Input Voltage (VI) 0V to VCC
Output Voltage (VO) 0V to VCC
Free Air Operating Temperature (TA)40 C to 85 C
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V
Symbol Parameter Conditions VCC Min Max Units
(V)
VIH HIGH Level Input Voltage 1.65 -1.95 0.65 x VCC
V2.3 - 2.7 1.7
2.7 - 3.6 2.0
VIL LOW Level Input Voltage 1.65 -1.95 0.35 x VCC
V2.3 - 2.7 0.7
2.7 - 3.6 0.8
VOH HIGH Level Output Voltage IOH 100 A 1.65 - 3.6 VCC - 0.2
V
IOH 4 mA 1.65 1.2
IOH 6 mA 2.3 2
IOH 12 mA 2.3 1.7
2.7 2.2
3.0 2.4
IOH 24 mA 3.0 2
VOL LOW Level Output Voltage IOL 100 A 1.65 - 3.6 0.2
V
IOL 4 mA 1.65 0.45
IOL 6 mA 2.3 0.4
IOL 12mA 2.3 0.7
2.7 0.4
IOL 24 mA 3 0.55
IIInput Leakage Current 0 VI 3.6V 3.6 5.0 A
IOZ 3-STATE Output Leakage 0 VO 3.6V 3.6 10 A
ICC Quiescent Supply Current VI VCC or GND, IO 0 3.6 40 A
ICC Increase in ICC per Input VIH VCC 0.6V 3 -3.6 750 A
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74ALVC16373
AC Electrical Characteristics
Capacitance
Symbol Parameter
T A 40 C to 85 C, RL 500
Units
CL 50 pF CL 30 pF
V CC 3.3V 0.3V V CC 2.7V V CC 2.5V 0.2V V CC 1.8V 0.15V
Min Max Min Max Min Max Min Max
tPHL, tPLH Propagation Delay 1.3 3.5 1.5 3.9 1.0 3.4 1.5 6.8 ns
Bus to Bus
tPHL, tPLH Propagation Delay 1.3 3.5 1.5 4.4 1.0 3.9 1.5 7.8 ns
LE to Bus
tPZL, tPZH Output Enable Time 1.3 4.0 1.5 5.1 1.0 4.6 1.5 9.2 ns
tPLZ, tPHZ Output Disable Time 1.3 4.0 1.5 4.3 1.0 3.8 1.5 6.8 ns
Symbol Parameter Conditions TA 25 C Units
VCC Typical
CIN Input Capacitance VI 0V or VCC 3.3 6 pF
COUT Output Capacitance VI 0V or VCC 3.3 7 pF
CPD Power Dissipation Capacitance Outputs Enabled f 10 MHz, CL 50 pF 3.3 20 pF
2.5 20
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74ALVC16373
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
TABLE 1. Values for Figure 1
TABLE 2. Variable Matrix
(Input Characteristics: f 1MHz; tr tf 2ns; Z0 50 )
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ VL
tPZH, tPHZ GND
Symbol VCC
3.3V 0.3V 2.7V 2.5V 0.2V 1.8V 0.15V
Vmi 1.5V 1.5V VCC/2 VCC/2
Vmo 1.5V 1.5V VCC/2 VCC/2
VXVOL 0.3V VOL 0.3V VOL 0.15V VOL 0.15V
VYVOH 0.3V VOH 0.3V VOH 0.15V VOH 0.15V
VL6V 6V VCC*2 VCC*2
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74ALVC16373
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
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74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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