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74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

May 2007

74VCX163245 Rev. 1.7

74VCX163245

Low Voltage 16-Bit Dual Supply Translating

Transceiver with 3-STATE Outputs

Features

■

Bidirectional interface between busses ranging from

1.65V to 3.6V

■

Supports Live Insertion and Withdrawal

(1)

■

Static Drive (I

)

– ±24mA @ 3.0V V

– ±18mA @ 2.3V V

– ±6mA @ 1.65V V

■

circuitry

■

Functionally compatible with 74 series 16245

■

Latchup performance exceeds 300mA

■

ESD performance:

– Human Body Model

2000V

– Machine model

200V

■

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note:

1. To ensure the high impedance state during power up

or power down, OE

should be tied to V

CCB

through a

pull up resistor. The minimum value of the resistor is

determined by the current sourcing capability of the

driver.

General Description

The VCX163245 is a dual supply, 16-bit translating

transceiver that is designed for 2 way asynchronous

communication between busses at different supply volt-

ages by providing true signal translation. The supply rails

consist of V

CCA

, which is a higher potential rail operating

at 2.3V to 3.6V and V

CCB

, which is the lower potential

rail operating at 1.65V to 2.7V. (V

CCB

must be less than

or equal to V

CCA

for proper device operation). This dual

supply design allows for translation from 1.8V to 2.5V

busses to busses at a higher potential, up to 3.3V.

The Transmit/Receive (T/R) input determines the direc-

tion of data flow. Transmit (active-HIGH) enables data

from A Ports to B Ports; Receive (active-LOW) enables

data from B Ports to A Ports. The Output Enable (OE)

input, when HIGH, disables both A and B Ports by plac-

ing them in a High-Z condition. The A Port interfaces

with the higher voltage bus (2.7V to 3.3V); The B Port

interfaces with the lower voltage bus (1.8V to 2.5V). Also

the VCX163245 is designed so that the control pins

(T/R

, OE

) are supplied by V

CCB

The 74VCX163245 is suitable for mixed voltage applica-

tions such as notebook computers using a 1.8V CPU and

3.3V peripheral components. It is fabricated with an

Advanced CMOS technology to achieve high speed oper-

ation while maintaining low CMOS power dissipation.

Ordering Information

Notes:

2. Ordering code “G” indicates Trays.

3. Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number Package Number Package Description

74VCX163245G

(2)(3)

BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205,

5.5mm Wide

74VCX163245MTD

(3)

MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC

MO-153, 6.1mm Wide

Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.

Uses proprietary Quiet Series™ noise/EMI reduction

7 V 7 I 2 G 4 5 S T/m—t 48—09 ( 000000 90—1 ‘7_An ‘11 000000 E‘—3 46—A‘ 0 000000 GND—A AS—GND 3 $88888 B2—5 “—A2 u oooooo 53—5 43—A3 L5 000000 VCCB—7 Az—vcCA I 000000 a—a H_A‘ 1 000000 55—9 AO—AS GNU—m 39—0ND as—H 38—A5 57—12 37—A7 aa—u 35—A8 39—1; 35—A9 GNU—15 Sl—GND am—ts 35—Am aH—n 32—AH Vcca— ”3 3‘ ‘VccA a‘z—te SO—A,Z B‘s—20 29—h GND—Z‘ ZE—GND EH—ZZ z7—AH E‘s—13 25—A‘5 V'RZ—u 25—07Z |||||||||||||||| ‘0 Al A2 A5 A4 A5 ‘5 A7 A8 ‘9 MAHAMAHAU’HS —o|0’E‘ 0E —T/§‘ T/EZ Bo 3‘ 52 33 as as 37 “a 59 Em BHE‘ZBHBH E‘s | ?

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 2

Connection Diagram

Pin Assignment for TSSOP Pin Assignment for FBGA

(Top Thru View)

FBGA Pin Assignments

Pin Descriptions

Logic Diagram

123456

NC T/R

NC A

NC NC A

CCB

CCA

GND GND A

CCB

CCA

NC NC A

NC T/R

NC A

Names

Description

Output Enable Input (Active LOW)

T/R

Transmit/Receive Input

–A

Side A Inputs or 3-STATE Outputs

–B

Side B Inputs or 3-STATE Outputs

NC No Connect

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 3

Truth Tables

HIGH Voltage Level

LOW Voltage Level

Immaterial (HIGH or LOW, inputs may not float)

High Impedance

VCX163245 Translator Power Up Sequence Recommendations

To guard against power up problems, some simple

guidelines need to be adhered to. The VCX163245 is

designed so that the control pins (T/R

, OE

) are sup-

plied by V

CCB

. Therefore the first recommendation is to

begin by powering up the control side of the device,

CCB

. The OE

control pins should be ramped with or

ahead of V

CCB

, this will guard against bus contentions

and oscillations as all A Port and B Port outputs will be

disabled. To ensure the high impedance state during

power up or power down, OE

should be tied to V

CCB

through a pull up resistor. The minimum value of the

resistor is determined by the current sourcing capability

of the driver. Second, the T/R

control pins should be

placed at logic LOW (0V) level, this will ensure that the

B-side bus pins are configured as inputs to help guard

against bus contention and oscillations. B-side Data

Inputs should be driven to a valid logic level (0V or

CCB

), this will prevent excessive current draw and oscil-

lations. V

CCA

can then be powered up after V

CCB

, how-

ever V

CCA

must be greater than or equal to V

CCB

ensure proper device operation. Upon completion of

these steps the device can then be configured for the

users desired operation. Following these steps will help

to prevent possible damage to the translator device as

well as other system components.

Logic Diagrams

Please note that these diagrams are provided only for the understanding of logic operations and should not be used

to estimate propagation delays.

Inputs

OutputsOE

T/R

LLBus B

–B

Data to Bus A

–A

LHBus A

–A

Data to Bus B

–B

HXHIGH Z State on A

–A

, B

–B

Inputs

OutputsOE

T/R

LLBus B

–B

Data to Bus A

–A

LHBus A8–A15 Data to Bus B8–B15

HXHIGH-Z State on A8–A15, B8–B15

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions(5)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Notes:

4. IO Absolute Maximum Rating must be observed.

5. Unused inputs or I/O pins must be held HIGH or LOW. They may not float.

6. Operation requires: VCCB ≤ VCCA

Symbol Parameter Rating

VCCA Supply Voltage –0.5V to +4.6V

VCCB –0.5V to VCCA

VIDC Input Voltage –0.5V to +4.6V

VI/O DC Output Voltage

Outputs 3-STATE –0.5V to +4.6V

An Output Active(4) –0.5V to VCCA + 0.5V

Bn Output Active(4) –0.5V to VCCB + 0.5V

IIK DC Input Diode Current, VI < 0V –50mA

IOK DC Output Diode Current

O < 0V –50mA

O > VCC +50mA

IOH/IOL DC Output Source/Sink Current ±50mA

DC VCC or Ground Current ±100mA

ICC or Ground Supply Pin

TSTG Storage Temperature –65°C to +150°C

Symbol Parameter Rating

VCCA Power Supply(6) 2.3V to 3.6V

VCCB 1.65V to 2.7V

VIInput Voltage () @ OE, T/R 0V to VCCB

VI/O Input/Output Voltage ()

0V to VCCA

0V to VCCB

IOH/IOL Output Current in IOH/IOL

VCCA = 3.0V to 3.6V ±24mA

VCCA = 2.3V to 2.7V ±18mA

VCCB = 2.3V to 2.7V ±18mA

VCCB = 1.65V to 1.95V ±6mA

TAFree Air Operating Temperature –40°C to +85°C

∆t/∆V Minimum Input Edge Rate, VIN = 0.8V to 2.0V, VCC = 3.0V 10ns/V

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 5

DC Electrical Characteristics (1.65V < VCCB ≤ 1.95V, 2.3V < VCCA ≤ 2.7V)

Symbol Parameter VCCB (V) VCCA (V) Conditions Min. Max. Units

VIHA HIGH Level Input

Voltage

An1.65–1.95 2.3–2.7 1.6 V

VIHB Bn, T/R, OE 1.65–1.95 2.3–2.7 0.65 x VCCB V

VILA LOW Level Input

Voltage

An1.65–1.95 2.3–2.7 0.7 V

VILB Bn, T/R, OE 1.65–1.95 2.3–2.7 0.35 x VCCB V

VOHA HIGH Level Output Voltage 1.65–1.95 2.3–2.7 IOH = –100µA VCCA – 0.2 V

1.65 2.3–2.7 IOH = –18mA 1.7

VOHB HIGH Level Output Voltage 1.65–1.95 2.3–2.7 IOH = –100µA VCCB – 0.2 V

1.65–1.95 2.3 IOH = –6mA 1.25

VOLA Low Level Output Voltage 1.65–1.95 2.3–2.7 IOL = 100µA 0.2 V

1.65 2.3–2.7 IOL = 18mA 0.6

VOLB Low Level Output Voltage 1.65–1.95 2.3–2.7 IOL = 100µA 0.2 V

1.65–1.95 2.3 IOL = 6mA 0.3

IIInput Leakage Current @ OE,

T/R

1.65–1.95 2.3–2.7 0V ≤ VI ≤ 3.6V ±5.0 µA

IOZ 3-STATE Output Leakage 1.65–1.95 2.3–2.7 0V ≤ VO ≤ 3.6V,

OE = VCCB,

VI = VIH or VIL

±10 µA

IOFF Power Off Leakage Current 0 0 0 ≤ (VI, VO) ≤ 3.6V 10 µA

ICCA/ICCB Quiescent Supply Current,

per supply, VCCA / VCCB

1.65–1.95 2.3–2.7 An = VCCA or GND,

Bn, OE, & T/R = V CCB

or GND

20 µA

1.65–1.95 2.3–2.7 VCCA ≤ An ≤ 3.6V,

VCCB ≤ Bn, OE,

T/R ≤ 3.6V

±20 µA

∆ICC Increase in ICC per Input, Bn,

T/R, OE

1.65–1.95 2.3–2.7 VI = VCCB – 0.6V 750 µA

Increase in ICC per Input, An1.65–1.95 2.3–2.7 VI = VCCA – 0.6V 750 µA

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 6

DC Electrical Characteristics (1.65V < VCCB ≤ 1.95V, 3.0V < VCCA ≤ 3.6V)

Symbol Parameter VCCB (V) VCCA (V) Conditions Min. Max. Units

VIHA HIGH Level Input

Voltage

An1.65–1.95 3.0–3.6 2.0 V

VIHB Bn, T/R, OE 1.65–1.95 3.0–3.6 0.65 x VCCB V

VILA LOW Level Input

Voltage

An1.65–1.95 3.0–3.6 0.8 V

VILB Bn, T/R, OE 1.65–1.95 3.0–3.6 0.35 x VCCB V

VOHA HIGH Level Output Voltage 1.65–1.95 3.0–3.6 IOH = –100µA VCCA – 0.2 V

1.65 3.0–3.6 IOH = –24mA 2.2

VOHB HIGH Level Output Voltage 1.65–1.95 3.0–3.6 IOH = –100µA VCCA – 0.2 V

1.65–1.95 3.0 IOH = –6mA 1.25

VOLA LOW Level Output Voltage 1.65–1.95 3.0–3.6 IOL = 100µA 0.2 V

1.65 3.0–3.6 IOL = 24mA 0.55

VOLB LOW Level Output Voltage 1.65–1.95 3.0–3.6 IOL = 100µA 0.2 V

1.65–1.95 3.0 IOL = 6mA 0.3

IIInput Leakage Current @ OE,

T/R

1.65–1.95 3.0–3.6 0V ≤ VI ≤ 3.6V ±5.0 µA

IOZ 3-STATE Output Leakage 1.65–1.95 3.0–3.6 0V ≤ VO ≤ 3.6V,

OE = VCCB,

VI = VIH or VIL

±10 µA

IOFF Power OFF Leakage Current 0 0 0 ≤ (VI, VO) ≤ 3.6V 10 µA

ICCA/ICCB Quiescent Supply Current,

per supply, VCCA/VCCB

1.65–1.95 3.0–3.6 An = VCCA or GND,

Bn, OE, & T/R = VCCB

or GND

20 µA

1.65–1.95 3.0–3.6 VCCA ≤ An ≤ 3.6V,

VCCB ≤ Bn, OE,

T/R ≤ 3.6V

±20 µA

∆ICC Increase in ICC per Input, Bn,

T/R, OE,

1.65–1.95 3.0–3.6 VI = VCCB – 0.6V 750 µA

Increase in ICC per Input, An1.65–1.95 3.0–3.6 VI = VCCA – 0.6V 750 µA

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 7

DC Electrical Characteristics (2.3V < VCCB ≤ 2.7V, 3.0V ≤ VCCA ≤ 3.6V)

Symbol Parameter VCCB (V) VCCA (V) Conditions Min. Max. Units

VIHA HIGH Level Input

Voltage

An2.3–2.7 3.0–3.6 2.0 V

VIHB Bn, T/R, OE 2.3–2.7 3.0–3.6 1.6 V

VILA LOW Level Input

Voltage

An2.3–2.7 3.0–3.6 0.8 V

VILB Bn, T/R, OE 2.3–2.7 3.0–3.6 0.7 V

VOHA HIGH Level Output Voltage 2.3–2.7 3.0–3.6 IOH = –100µA VCCA – 0.2 V

2.3 3.0–3.6 IOH = –24mA 2.2

VOHB HIGH Level Output Voltage 2.3–2.7 3.0–3.6 IOH = –100µA VCCB – 0.2 V

2.3–2.7 3.0 IOH = –18mA 1.7

VOLA LOW Level Output Voltage 2.3–2.7 3.0–3.6 IOL = 100µA 0.2 V

2.3 3.0–3.6 IOL = 24mA 0.55

VOLB LOW Level Output Voltage 2.3–2.7 3.0–3.6 IOL = 100µA 0.2 V

2.3–2.7 3.0 IOL = 18mA 0.6

IIInput Leakage Current @ OE,

T/R

2.3–2.7 3.0–3.6 0V ≤ VI ≤ 3.6V ±5.0 µA

IOZ 3-STATE Output Leakage @ An2.3–2.7 3.0–3.6 0V ≤ VO ≤ 3.6V,

OE = VCCA,

VI = VIH or VIL

±10 µA

IOFF Power OFF Leakage Current 0 0 0 ≤ (VI, VO) ≤ 3.6V 10 µA

ICCA/ICCB Quiescent Supply Current,

per supply, VCCA/VCCB

2.3–2.7 3.0–3.6 An = VCCA or GND,

Bn, OE, & T/R = VCCB

or GND

20 µA

2.3–2.7 3.0–3.6 VCCA ≤ An ≤ 3.6V,

VCCB ≤ Bn, OE,

T/R ≤ 3.6V

±20 µA

∆ICC Increase in ICC per Input, Bn,

T/R, OE

2.3–2.7 3.0–3.6 VI = VCCB – 0.6V 750 µA

Increase in ICC per Input, An2.3–2.7 3.0–3.6 VI = VCCA – 0.6V 750 µA

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 8

AC Electrical Characteristics

Note:

7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (tosHL) or LOW-to-HIGH (tosLH).

Dynamic Switching Characteristics

Symbol Parameter

TA = –40°C to +85°C, CL = 30 pF, RL = 500Ω

Units

VCCB = 1.65V to 1.95V,

VCCA = 2.3V to 2.7V

VCCB = 1.65V to 1.95V,

VCCA = 3.0V to 3.6V

VCCB = 2.3V to 2.7V,

VCCA = 3.0V to 3.6V

Min. Max. Min. Max. Min. Max.

tPHL, tPLH Propagation Delay,

A to B

1.5 5.8 1.5 6.2 0.8 4.4 ns

tPHL, tPLH Propagation Delay,

B to A

0.8 5.5 0.6 5.1 0.6 4.0 ns

tPZL, tPZH Output Enable Time,

OE to B

1.5 8.3 1.5 8.2 0.8 4.6 ns

tPZL, tPZH Output Enable Time,

OE to A

0.8 5.3 0.6 5.1 0.6 4.0 ns

tPLZ, tPHZ Output Disable Time,

OE to B

0.8 4.6 0.8 4.5 0.8 4.4 ns

tPLZ, tPHZ Output Disable Time,

OE to A

0.8 5.2 0.6 5.6 0.6 4.8 ns

tosHL, tosLH Output to Output

Skew(7) 0.05 0.5 0.75 ns

Symbol Parameter VCCB (V) VCCA (V) Conditions

TA = +25°C

Typical Units

VOLP Quiet Output Dynamic

Peak VOL, A to B

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

0.25 V

1.8 3.3 0.25

2.5 3.3 0.6

VOLP Quiet Output Dynamic

Peak VOL, B to A

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

0.6 V

1.8 3.3 0.8

2.5 3.3 0.8

VOLV Quiet Output Dynamic

Valley VOL, A to B

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

–0.25 V

1.8 3.3 –0.25

2.5 3.3 –0.6

VOLV Quiet Output Dynamic

Valley VOL, B to A

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

–0.6 V

1.8 3.3 –0.8

2.5 3.3 –0.8

VOHV Quiet Output Dynamic

Valley VOH, A to B

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

1.3 V

1.8 3.3 1.3

2.5 3.3 1.7

VOHV Quiet Output Dynamic

Valley VOH, B to A

1.8 2.5 CL = 30 pF, VIH = VCC,

VIL = 0V

1.7 V

1.8 3.3 2.0

2.5 3.3 2.0

TEST 0— S‘GNAL o— DATA v VCC ‘N m‘ GNU ‘W 1p“ DATA V OUT W owur v VCC CONTROL "“ 5ND ‘qu ‘PHZ + v DATA 9—' 0“ our VW CVV 0— OPEN 0— GND «PM, 1sz 6.0V or vcc'z tpzmm ‘PLw ‘PHL soon owur v VCC CONTROL "“ 5ND ‘PzL ‘PLz + DATA v Vm

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 9

Capacitance

AC Loading and Waveforms

Figure 1. AC Test Circuit

Figure 2. Waveform for Inverting

and Non-inverting Functions

tR = tF ≤ 2.0 ns, 10% to 90%

Figure 3. 3-STATE Output High Enable and Disable

Times for Low Voltage Logic

tR = tF ≤ 2.0 ns, 10% to 90%

Figure 4. 3-STATE Output Low Enable and Disable

Times for Low Voltage Logic

tR = tF ≤ 2.0 ns, 10% to 90%

Symbol Parameter Conditions TA = +25°C Units

CIN Input Capacitance VCCB = 2.5V, VCCA = 3.3V, VI = 0V

or VCCA/B

5pF

CI/O Input/Output Capacitance VCCB = 2.5V, VCCA = 3.3V, VI = 0V

or VCCA/B

6pF

CPD Power Dissipation Capacitance VCCB = 2.5V, VCCA = 3.3V,

VI = 0V or VCCA/B, f = 10MHz

20 pF

Test Switch

tPLH, tPHL OPEN

tPZL, tPLZ 6V at VCC = 3.3 ±0.3V;

VCC x 2 at VCC = 2.5 ± 0.2V;

1.8V ± 0.15V

tPZH, tPHZ GND

Symbol

VCC

3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V

Vmi 1.5V VCC / 2 VCC / 2

Vmo 1.5V VCC / 2 VCC / 2

VXVOL + 0.3V VOL + 0.15V VOL + 0.15V

VYVOH – 0.3V VOH – 0.15V VOH – 0.15V

El —(o.3) o o °i° o 0 990699— ooolooo ooolooo ooolooo— O OiOOC g /— PIN ONE ABCDEFGHJ El 123I456 I Top +005 Bottom View 54x 0.54.05 View 4} 0.1564) c AIBI 0.08® c NOTES: A. THIS PACKAGE CONFORMS TO JEDEC M0-205 B. ALL DIMENSIONS IN MILLIMETERS C. LAND PA'I'I'ERN RECOMMENDATION: NSMD (Non Solder Mask Deﬁned .SSMM DIA PADS WITH A SOLDERMASK OPENING OF .45MM CONCE TRIC TO PADS D. DRAWING CONFORMS TO ASME Y14.5M-1994 BGA54ArevD

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 10

Physical Dimensions

Dimensions are in millimeters unless otherwise noted.

Figure 5. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

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74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 11

Physical Dimensions (Continued)

Dimensions are in millimeters unless otherwise noted.

Figure 6. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

— FAIRCHILD — saw _ Nnucmw

74VCX163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74VCX163245 Rev. 1.7 12

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