74LVX541 by STMicroelectronics Datasheet | DigiKey

74LVX541 Datasheet by STMicroelectronics

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1/12August 2004
■HIGH SPEED:
tPD = 5.0 ns (TYP.) at VCC = 3.3V
■5V TOLERANT INPUTS
■POWER-DOWN PROTECTION ON INPUTS
■INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V
■LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
■LOW NOISE:
VOLP = 0.3V (TYP.) at VCC =3.3V
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC =3V
■BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
■OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541
■IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX541 is a low voltage CMOS OCTAL
BUS BUFFER with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The 3 STATE control gate operates as two input
AND such that if either G1 or G2 are high, all eight
outputs are in the high impedance state.
In order to enhance PC board layout, the
74VHC541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX541
LOW VOLTAGE CMOS OCTAL BUS BUFFER
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX541MTR
TSSOP 74LVX541TTR
TSSOPSOP
Rev. 2
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74LVX541
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Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table
X : Don’t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
PIN N° SYMBOL NAME AND FUNCTION
1, 19 G1, G2 Output Enable Inputs
2, 3, 4, 5, 6,
7, 8, 9 A1 to A8 Data Inputs
18, 17, 16,
15, 14, 13,
12, 11
Y1 to Y8 Data Outputs
10 GND Ground (0V)
20 VCC Positive Supply Voltage
INPUT OUTPUT
G1 G2 An Yn
HXXZ
XHXZ
LLHH
LLLL
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7.0 V
VIDC Input Voltage -0.5 to +7.0 V
VODC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current - 20 mA
IOK DC Output Diode Current ± 20 mA
IODC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature (10 sec) 300 °C
Symbol Parameter Value Unit
VCC Supply Voltage (note 1) 2 to 3.6 V
VIInput Voltage 0 to 5.5 V
VOOutput Voltage 0 to VCC V
Top Operating Temperature -55 to 125 °C
dt/dv Input Rise and Fall Time (note 2) (VCC = 3V) 0 to 100 ns/V
£1
74LVX541
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Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage 2.0 1.5 1.5 1.5
V3.0
2.0 2.0 2.0
3.6
2.4 2.4 2.4
VIL Low Level Input
Voltage 2.0 0.5 0.5 0.5
V3.0 0.8 0.8 0.8
3.6 0.8 0.8 0.8
VOH High Level Output
Voltage 2.0 IO=-50 µA1.9 2.0 1.9 1.9
V3.0 IO=-50 µA2.9 3.0 2.9 2.9
3.0 IO=-4 mA 2.58 2.48 2.4
VOL Low Level Output
Voltage 2.0 IO=50 µA0.0 0.1 0.1 0.1
V3.0 IO=50 µA0.0 0.1 0.1 0.1
3.0 IO=4 mA 0.36 0.44 0.55
IOZ High Impedance
Output Leakage
Current 3.6 VI = VIH or VIL
VO = VCC or GND ±0.25 ± 2.5 ± 2.5 µA
IIInput Leakage
Current 3.6 VI = 5V or GND ± 0.1 ± 1 ± 1 µA
ICC Quiescent Supply
Current 3.6 VI = VCC or GND 44040µA
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VOLP Dynamic Low
Voltage Quiet
Output (note 1, 2) 3.3
CL = 50 pF
0.3 0.8
V
VOLV -0.8 -0.3
VIHD
Dynamic High
Voltage Input
(note 1, 3) 3.3 2.0
VILD
Dynamic Low
Voltage Input
(note 1, 3) 3.3 0.8
E]
74LVX541
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Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
Table 9: Capacitive Characteristics
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
Symbol Parameter
Test Condition Value
Unit
VCC
(V) CL
(pF)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
tPLH
tPHL
Propagation Delay
Time 2.7 15 6.3 8.3 1.0 10.0 1.0 10.0
ns
2.7 50 9.0 12.0 1.0 15.0 1.0 15.0
3.3(*) 15 5.0 7.0 1.0 8.5 1.0 8.5
3.3(*) 50 7.5 10.5 1.0 12.0 1.0 12.0
tPZL
tPZH
Output Enable
Time 2.7 15 8.0 12.0 1.0 14.0 1.0 14.0
ns
2.7 50 11.0 15.0 1.0 16.0 1.0 16.0
3.3(*) 15 6.8 10.8 1.0 12.5 1.0 12.5
3.3(*) 50 9.3 14.0 1.0 16.0 1.0 16.0
tPLZ
tPHZ
Output Disable
Time
2.7 50 12.5 16.5 1.0 19.0 1.0 19.0 ns
3.3(*) 50 11.2 15.4 1.0 17.5 1.0 17.5
tOSLH
tOSHL
Output to Output
Skew Time (note
1,2)
2.7 50 0.5 1.0 1.5 1.5 ns
3.3(*) 50 0.5 1.0 1.5 1.5
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 3.3 7 10 10 10 pF
COUT Output
Capacitance 3.3 9 pF
CPD Power Dissipation
Capacitance
(note 1) 3.3 fIN = 10MHz 20 pF
PULSE GENERATOR , SCH7OO O— Vcc OiOPEN 0— GND Ens 3ns scosssa £1
74LVX541
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Figure 3: Test Circuit
CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ VCC
tPZH, tPHZ GND
3n: 3H5 aii fiik 90% 90% 51.32 50% 50% 10% 7 10% {pm ‘PHZ W‘ 50% tPZL 4‘ ‘7 *PLZ 50% Yr! Sclésto 0ND VoH vOH —0‘3v 6ND v0L +0.3v VoL
74LVX541
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Figure 5: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
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74LVX541
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DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.1 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.60 13.00 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
k0°8°0°8°
ddd 0.100 0.004
SO-20 MECHANICAL DATA
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74LVX541
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DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0˚ 8˚0˚ 8˚
L 0.45 0.60 0.75 0.018 0.024 0.030
TSSOP20 MECHANICAL DATA
cE
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1 L
K
e
0087225C
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74LVX541
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DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197
Ao 10.8 11 0.425 0.433
Bo 13.2 13.4 0.520 0.528
Ko 3.1 3.3 0.122 0.130
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Tape & Reel SO-20 MECHANICAL DATA
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74LVX541
10/12
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882
Ao 6.8 7 0.268 0.276
Bo 6.9 7.1 0.272 0.280
Ko 1.7 1.9 0.067 0.075
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Tape & Reel TSSOP20 MECHANICAL DATA
£1
74LVX541
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Table 10: Revision History
Date Revision Description of Changes
27-Aug-2004 2 Ordering Codes Revision - pag. 1.
E]
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