74LVX374 by STMicroelectronics Datasheet | DigiKey

74LVX374 Datasheet by STMicroelectronics

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1/10July 2001
■HIGH SPEED:
fMAX = 160MHz (TYP.) at VCC = 3.3V
■5V TOLERANT INPUTS
■POWER-DOWN PROTECTION ON INPUTS
■INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V
■LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
■LOW NOISE:
VOLP = 0.3V (TYP.) at VCC =3.3V
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC =3V
■BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
■OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
■IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX374 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE). On
the positive transition of the clock, the Q outputs
will be set to the logic state that were setup at the
D inputs. While the (OE) input is low, the 8 outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state. The output control does not
affect the internal operation of flip flops; that is,
the old data can be retained or the new data can
be entered even while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX374
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVX374M 74LVX374MTR
TSSOP 74LVX374TTR
TSSOPSOP
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74LVX374
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No SYMBOL NAME AND FUNCTION
1OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9, 12,
15, 16,19 Q0 to Q7 3-State Outputs
3, 4, 7, 8, 13,
14, 17, 18 D0 to D7 Data Inputs
11 CK Clock
10 GND Ground (0V)
20 VCC Positive Supply Voltage
INPUTS OUTPUT
OE CK D Q
HXXZ
L X NO CHANGE
LLL
LHH
74LVX374
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
DC SPECIFICATIONS
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7.0 V
VIDC Input Voltage -0.5 to +7.0 V
VODC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current - 20 mA
IOK DC Output Diode Current ± 20 mA
IODC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature (10 sec) 300 °C
Symbol Parameter Value Unit
VCC Supply Voltage (note 1) 2 to 3.6 V
VIInput Voltage 0 to 5.5 V
VOOutput Voltage 0 to VCC V
Top Operating Temperature -55 to 125 °C
dt/dv Input Rise and Fall Time (note 2) (VCC = 3V) 0 to 100 ns/V
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage 2.0 1.5 1.5 1.5
V3.0
2.0 2.0 2.0
3.6
2.4 2.4 2.4
VIL Low Level Input
Voltage 2.0 0.5 0.5 0.5
V3.0 0.8 0.8 0.8
3.6 0.8 0.8 0.8
VOH High Level Output
Voltage 2.0 IO=-50 µA1.9 2.0 1.9 1.9
V3.0 IO=-50 µA2.9 3.0 2.9 2.9
3.0 IO=-4 mA 2.58 2.48 2.4
VOL Low Level Output
Voltage 2.0 IO=50 µA0.0 0.1 0.1 0.1
V3.0 IO=50 µA0.0 0.1 0.1 0.1
3.0 IO=4 mA 0.36 0.44 0.55
IOZ High Impedance
Output Leakage
Current 3.6 VI = VIH or VIL
VO = VCC or GND ±0.25 ± 2.5 ± 5 µA
IIInput Leakage
Current 3.6 VI = 5V or GND ± 0.1 ± 1 ± 1 µA
ICC Quiescent Supply
Current 3.6 VI = VCC or GND 44040µA
£7
74LVX374
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DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VOLP Dynamic Low
Voltage Quiet
Output (note 1, 2) 3.3
CL = 50 pF
0.3 0.8
V
VOLV -0.8 -0.3
VIHD
Dynamic High
Voltage Input
(note 1, 3) 3.3 2.0
VILD
Dynamic Low
Voltage Input
(note 1, 3) 3.3 0.8
Symbol Parameter
Test Condition Value
Unit
VCC
(V) CL
(pF)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
tPLH
tPHL
Propagation Delay
Time
CK to Q
2.7 15 8.5 16.3 1.0 19.5 1.0 20.5
ns
2.7 50 11.0 19.8 1.0 23.0 1.0 24.0
3.3(*) 15 6.7 10.6 1.0 12.5 1.0 13.5
3.3(*) 50 9.2 14.1 1.0 16.0 1.0 17.0
tPZL
tPZH
Output Enable
Time 2.7 15 7.6 14.5 1.0 17.5 1.0 18.5
ns
2.7 50 10.1 18.0 1.0 21.0 1.0 22.0
3.3(*) 15 5.9 9.3 1.0 11.0 1.0 12.0
3.3(*) 50 8.4 12.8 1.0 14.5 1.0 15.5
tPLZ
tPHZ
Output Disable
Time
2.7 50 11.5 18.5 1.0 22.0 1.0 23.0 ns
3.3(*) 50 9.6 13.2 1.0 15.0 1.0 16.0
tWCK pulse Width,
HIGH
2.7 50 7.5 8.0 8.0 ns
3.3(*) 50 5.0 5.5 5.5
tSSetup Time D to CK
HIGH or LOW
2.7 50 6.5 6.5 6.5 ns
3.3(*) 50 4.5 4.5 4.5
thHold Time D to CK
HIGH or LOW
2.7 50 2.0 2.0 2.0 ns
3.3(*) 50 2.0 2.0 2.0
fMAX Maximum Clock
Frequency 2.7 15 60 115 50 45
MHz
2.7 50 45 60 40 35
3.3(*) 15 100 160 85 75
3.3(*) 50 60 95 55 50
tOSLH
tOSHL
Output to Output
Skew Time (note
1,2)
2.7 50 0.5 1.0 1.5 1.5 ns
3.3(*) 50 0.5 1.0 1.5 1.5
PULSE GENERATOR SCI I700 Ochc O—OFEN OiGND
74LVX374
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CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
TEST CIRCUIT
CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 3.3 4101010pF
C
OUT Output
Capacitance 3.3 6 pF
CPD Power Dissipation
Capacitance
(note 1) 3.3 fIN = 10MHz 32 pF
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ VCC
tPZH, tPHZ GND
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74LVX374
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WAVEFORM 1 : PROPAGATION DELAYS SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
Ens 3n: CK 50% 50% GND sc09271
74LVX374
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WAVEFORM 3 : MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
74LVX374
8/10
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
M 0.75 0.029
S8° (max.)
SO-20 MECHANICAL DATA
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74LVX374
9/10
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
TSSOP20 MECHANICAL DATA
cE
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1 L
K
e
0087225C
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74LVX374
10/10
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
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