1. General description
The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with
two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions
(nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on
the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the
HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used
as the clock input to the counter. The other clock input may be used as a clock enable
input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and
nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4520: CMOS level
For 74HCT4520: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Rev. 3 — 4 December 2014 Product data sheet
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 2 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74HC4520N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4520N
74HC4520D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT4520D
74HC4520DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT4520DB
74HC4520PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Functional diagram
001aae698
1CP0
1
1CP12
1MR7
31Q0
41Q1
51Q2
61Q3
2CP0
9
2CP110
2MR15
112Q0
122Q1
132Q2
142Q3
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 3 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Fig 2. Timing diagram
001aae707
nCP0
nCP1
nMR
nQ0
123456789101112131415161718
12345678910111213141501234
nQ1
nQ2
nQ3
Fig 3. Logic diagram for one counter
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 4 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Pin configuration DIP16 Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16
and SSOP16
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Table 2. Pin description
Symbol Pin Description
1CP0, 2CP0 1, 9 clock input (LOW-to-HIGH edge-triggered)
1CP1, 2CP1 2, 10 clock input (HIGH-to-LOW edge-triggered)
1Q0 to 1Q3 3, 4, 5, 6 output
1MR, 2MR 7, 15 asynchronous master reset input (active HIGH)
GND 8 ground (0 V)
2Q0 to 2Q3 11, 12, 13, 14 output
VCC 16 supply voltage
la,
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 5 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition.
8. Limiting values
[1] For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
Table 3. Function table[1]
nCP0 nCP1nMR Mode
H L counter advances
LL counter advances
X L no change
XL no change
L L no change
HL no change
X X H nQ0 to nQ3 = LOW
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current VO= 0.5 V to VCC + 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [1] -750mW
SO16 package [1] -500mW
(T)SSOP16 package [1] -500mW
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 6 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC4520 74HCT4520 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC4520
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO=4.0mA; V
CC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80.0 - 160.0 A
Figure 8
Figure 7
Figure 7
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 7 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
11. Dynamic characteristics
CIinput
capacitance -3.5- - - - -pF
74HCT4520
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A 4.4 4.5 - 4.4 - 4.4 - V
IO=4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =5.5V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80.0 - 160.0 A
ICC additional
supply current per input pin; VI=V
CC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO=0A
pin nCP0, nCP1 - 80 288 - 360 - 392 A
pin nMR - 150 540 - 675 - 735 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC4520
tpd propagation
delay nCP0 to nQn; see Figure 7 [1]
VCC = 2.0 V - 77 240 - 300 - 360 ns
VCC = 4.5 V - 28 48 - 60 - 72 ns
VCC = 5.0 V; CL=15pF - 24 - - - - - ns
VCC = 6.0 V - 22 41 - 51 - 61 ns
nCP1 to nQn; see Figure 7 [1]
VCC = 2.0 V - 77 240 - 300 - 360 ns
VCC = 4.5 V - 28 48 - 60 - 72 ns
VCC = 5.0 V; CL=15pF - 24 - - - - - ns
VCC = 6.0 V - 22 41 - 51 - 61 ns
Figrea
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 8 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
tPHL HIGH to LOW
propagation
delay
nMR to nQn; see Figure 7
VCC = 2.0 V - 44 150 - 190 - 225 ns
VCC = 4.5 V - 16 30 - 38 - 45 ns
VCC = 5.0 V; CL=15pF - 13 - - - - - ns
VCC = 6.0 V - 13 26 - 33 - 38 ns
tttransition
time nQn; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns
tWpulse width nCP0, nCP1 HIGH or LOW; see Figure 7
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC =4.5V 16 8 - 20 - 24 - ns
VCC =6.0V 14 6 - 17 - 20 - ns
nMR HIGH; see Figure 7
VCC = 2.0 V 120 39 - 150 - 180 - ns
VCC =4.5V 24 14 - 30 - 36 - ns
VCC =6.0V 20 11 - 26 - 31 - ns
trec recovery time nMR to nCP0, nCP1; see Figure 7
VCC =2.0V 0 28 - 0 - 0 - ns
VCC =4.5V 0 10 - 0 - 0 - ns
VCC =6.0V 0 8- 0 - 0 - ns
tsu set-up time nCP0 to nCP1; nCP1 to nCP0; see Figure 7
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC =4.5V 16 5 - 20 - 24 - ns
VCC =6.0V 14 4 - 17 - 20 - ns
fmax maximum
frequency nCP0, nCP1; see Figure 7
VCC = 2.0 V 6 19 - 4.8 - 4 - MHz
VCC =4.5V 30 58 - 24 - 20 - MHz
VCC = 5.0 V; CL=15pF - 68 - - - - - MHz
VCC =6.0V 35 69 - 28 - 24 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC; VCC =5V;
fi=1MHz
[3] -29- - - - - pF
74HCT4520
tpd propagation
delay nCP0 to nQn; see Figure 7 [1]
VCC = 4.5 V - 28 53 - 66 - 80 ns
VCC = 5.0 V; CL=15pF - 24 - - - - - ns
nCP1 to nQn; see Figure 7 [1]
VCC = 4.5 V - 25 53 - 66 - 80 ns
VCC = 5.0 V; CL=15pF - 24 - - - - - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Figrea
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 9 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
tPHL HIGH to LOW
propagation
delay
nMR to nQn; see Figure 7
VCC = 4.5 V - 16 35 - 44 - 53 ns
VCC = 5.0 V; CL=15pF - 13 - - - - - ns
tttransition
time nQn; see Figure 7 [2]
VCC =4.5V - 7 15 - 19 - 22 ns
tWpulse width nCP0, nCP1 HIGH or LOW; see Figure 7
VCC =4.5V 20 10 - 25 - 30 - ns
nMR HIGH; see Figure 7
VCC =4.5V 20 12 - 25 - 30 - ns
trec recovery time nMR to nCP0, nCP1; see Figure 7
VCC =4.5V 0 8- 0 - 0 - ns
tsu set-up time nCP0 to nCP1; nCP1 to nCP0; see Figure 7
VCC =4.5V 16 6 - 20 - 24 - ns
fmax maximum
frequency nCP0, nCP1; see Figure 7
VCC =4.5V 30 58 - 24 - 20 - MHz
VCC = 5.0 V; CL=15pF - 64 - - - - - MHz
CPD power
dissipation
capacitance
VI=GNDtoV
CC 1.5 V;
VCC =5V; f
i=1MHz
[3] -24- - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 10 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
12. Waveforms
a. nCP0 and nCP1 set-up times, propagation delays and output transition times
b. nMR recovery time, minimum nCP0, nCP1, nMR pulse widths and maximum frequency
Measurement points are given in Table 8.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig 7. Waveforms showing measurements for switching times
001aae702
VI
VI
VI
VM
VM
VM
VM
tt
tsu tsu
tt
tPHL tPLH
90 %
10 %
tPHL
VOH
nCP0 input
nCP1 input
nMR input
nQn output
0 V
0 V 0 V
0 V
VOL
001aae701
nCP1 input
(nCP0 = LOW)
nCP0 input
(nCP1 = HIGH)
nMR input
V
M
V
I
0 V
V
I
0 V
V
I
0 V
t
W
1/f
max
V
M
t
W
V
M
t
W
t
rec
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 11 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Table 8. Measurement points
Type Input Output
VMVIVM
74HC4520 0.5 VCC GND to VCC 0.5 VCC
74HCT4520 1.3 V GND to 3 V 1.3 V
Test data is given in Table 9.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig 8. Test circuit for measuring switching times
9
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Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC4520 VCC 6ns 15pF, 50 pF 1kopen
74HCT4520 3 V 6 ns 15 pF, 50 pF 1 kopen
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 12 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
13. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 13 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 14 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 15 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
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74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 16 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4520 v.3 20141204 Product data sheet - 74HC_HCT4520_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4520_CNV v.2 19930927 Product specification - -
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 17 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com
salesaddresses®nx9£0m
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 4 December 2014 18 of 19
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 December 2014
Document identifier: 74HC_HCT4520
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
17 Contact information. . . . . . . . . . . . . . . . . . . . . 18
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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