74HC40103 Datasheet by NXP USA Inc.

Datasheet Feedback/Errors

PHILIPS

1. General description

The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the

40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC

standard no. 7A.

The 74HC40103 consists of an 8-bit synchronous down counter with a single output which

is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary

counter and has control inputs for enabling or disabling the clock (CP), for clearing the

counter to its maximum count and for presetting the counter either synchronously or

asynchronously. All control inputs and the terminal count output (TC) are active-LOW

logic.

In normal operation, the counter is decremented by one count on each positive-going

transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is

HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is

LOW, and remains LOW for one full clock period.

When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7)

is clocked into the counter on the next positive-going clock transition regardless of the

state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam

input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE,

TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.

When the master reset input (MR) is LOW, the counter is asynchronously cleared to its

maximum count (decimal 255) regardless of the state of any other input.

If all control inputs except TE are HIGH at the time of zero count, the counters will jump to

the maximum count, giving a counting sequence of 256 clock pulses long.

The 74HC40103 may be cascaded using the TE input and the TC output, in either a

synchronous or ripple mode.

74HC40103

8-bit synchronous binary down counter

Rev. 03 — 12 November 2004 Product data sheet

Product data sheet Rev. 03 — 12 November 2004 2 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

2. Features

■Cascadable

■Synchronous or asynchronous preset

■Low-power dissipation

■Complies with JEDEC standard no. 7A

■ESD protection:

◆HBM EIA/JESD22-A114-B exceeds 2000 V

◆MM EIA/JESD22-A115-A exceeds 200 V.

■Multiple package options

■Specified from −40 °Cto+80°C and from −40 °C to +125 °C.

3. Applications

■Divide-by-n counters

■Programmable timers

■Interrupt timers

■Cycle/program counters.

4. Quick reference data

[1] CPD is used to determine the dynamic power dissipation (PD in µW).

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

Table 1: Quick reference data

GND = 0 V; T

amb

=25

C; t

= 6 ns.

Symbol Parameter Conditions Min Typ Max Unit

tPHL, tPLH propagation delay CP to TC CL= 15 pF;

VCC = 5 V -30-ns

fmax maximum clock frequency CL= 15 pF;

VCC = 5 V - 32 - MHz

CIinput capacitance - 3.5 - pF

CPD power dissipation

capacitance VI= GND to VCC [1] -24-pF

Product data sheet Rev. 03 — 12 November 2004 3 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

5. Ordering information

6. Functional diagram

Table 2: Ordering information

Type number Package

Temperature range Name Description Version

74HC40103N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HC40103D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body

width 3.9 mm SOT109-1

74HC40103DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

74HC40103PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

Fig 1. Functional diagram Fig 2. Logic symbol

001aab923

P7 13

1CP

001aab921

Product data sheet Rev. 03 — 12 November 2004 4 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Fig 3. IEC logic symbol

Fig 4. Timing diagram

001aab922

2CT = 255

9C3 / G4

15 G2

3EN1

11, 2, 4-

2C3

3CT

1CT = 0

CTR8

001aab925

count 255 254 32102552542542538 7654255254253252

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 03 — 12 November 2004 5 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Fig 5. Logic diagram

001aab924

to other 7

flip-flops

PE PL CP MR

PE TE

jjjjjjjj EEEEEEEE ,7

Product data sheet Rev. 03 — 12 November 2004 6 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

7. Pinning information

7.1 Pinning

7.2 Pin description

Fig 6. Pin configuration

40103

CP VCC

MR PE

TE TC

P0 P7

P1 P6

P2 P5

P3 P4

GND PL

001aab920

Table 3: Pin description

Symbol Pin Description

CP 1 clock input (LOW-to-HIGH, edge-triggered)

MR 2 asynchronous master reset input (active LOW)

TE 3 terminal enable input (active LOW)

P0 4 jam input 0

P1 5 jam input 1

P2 6 jam input 2

P3 7 jam input 3

GND 8 ground (0 V)

PL 9 asynchronous preset enable input (active LOW)

P4 10 jam input 4

P5 11 jam input 5

P5 12 jam input 6

P7 13 jam input 7

TC 14 terminal count output (active LOW)

PE 15 synchronous preset enable input (active LOW)

VCC 16 positive supply voltage

Product data sheet Rev. 03 — 12 November 2004 7 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

8. Functional description

8.1 Function table

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

[2] Clock connected to CP.

Synchronous operation: changes occur on the LOW-to-HIGH CP transition.

Jam inputs: MSD = P7, LSD = P0.

9. Limiting values

[1] Above 70 °C: Ptot derates linearly with 12 mW/K.

[2] Above 70 °C: Ptot derates linearly with 8 mW/K.

Table 4: Function table[1]

Control inputs Preset mode Action [2]

MR PL PE TE

L X X X asynchronous clear to maximum count

H L X X asynchronous preset asynchronously

H L X synchronous preset on next LOW-to HIGH clock transition

H L synchronous count down

H synchronous inhibit counter

Table 5: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input diode current VI < −0.5 V or VI>V

CC + 0.5 V - ±20 mA

IOK output diode current VO<−0.5 V or

VO>V

CC + 0.5 V -±20 mA

IOoutput source or sink

current VO = −0.5 V to VCC + 0.5 V - ±25 mA

ICC, IGND VCC or GND current - ±50 mA

Tstg storage temperature −65 +150 °C

Ptot power dissipation

DIP16 package [1] - 750 mW

SO16, SSOP16 and

TSSOP16 packages

[2] - 500 mW

Product data sheet Rev. 03 — 12 November 2004 8 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

10. Recommended operating conditions

11. Static characteristics

Table 6: Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.0 5.0 6.0 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

tr, tfinput rise and fall times VCC = 2.0 V - - 1000 ns

VCC = 4.5 V - 6.0 500 ns

VCC = 6.0 V - - 400 ns

Tamb ambient temperature −40 - +125 °C

Table 7: Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb =25°C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V

VCC = 4.5 V 3.15 2.4 - V

VCC = 6.0 V 4.2 3.2 - V

VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V

VCC = 4.5 V - 2.1 1.35 V

VCC = 6.0 V - 2.8 1.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−20 µA; VCC = 2.0 V 1.9 2.0 - V

IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V

IO=−20 µA; VCC = 6.0 V 5.9 6.0 - V

IO=−4 mA; VCC = 4.5 V 3.98 4.32 - V

IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - V

VOL LOW-level output voltage VI=V

IH or VIL

IO=20µA; VCC = 2.0 V - 0 0.1 V

IO=20µA; VCC = 4.5 V - 0 0.1 V

IO=20µA; VCC = 6.0 V - 0 0.1 V

IO= 4 mA; VCC = 4.5 V - 0.15 0.26 V

IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 V

ILI input leakage current VI=V

CC or GND; VCC = 6.0 V - - ±0.1 µA

ICC quiescent supply current VI=V

CC or GND; IO= 0 A; VCC = 6.0 V - - 8.0 µA

CIinput capacitance - 3.5 - pF

Product data sheet Rev. 03 — 12 November 2004 9 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Tamb =−40 °C to +85 °C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V

VCC = 4.5 V 3.15 - - V

VCC = 6.0 V 4.2 - - V

VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V

VCC = 4.5 V - - 1.35 V

VCC = 6.0 V - - 1.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−20 µA; VCC = 2.0 V 1.9 - - V

IO=−20 µA; VCC = 4.5 V 4.4 - - V

IO=−20 µA; VCC = 6.0 V 5.9 - - V

IO=−4 mA; VCC = 4.5 V 3.84 - - V

IO=−5.2 mA; VCC = 6.0 V 5.34 - - V

VOL LOW-level output voltage VI=V

IH or VIL

IO=20µA; VCC = 2.0 V - - 0.1 V

IO=20µA; VCC = 4.5 V - - 0.1 V

IO=20µA; VCC = 6.0 V - - 0.1 V

IO= 4 mA; VCC = 4.5 V - - 0.33 V

IO= 5.2 mA; VCC = 6.0 V - - 0.33 V

ILI input leakage current VI=V

CC or GND; VCC = 6.0 V - - ±1.0 µA

ICC quiescent supply current VI=V

CC or GND; IO= 0 A; VCC = 6.0 V - - 80 µA

Tamb =−40 °C to +125 °C

VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V

VCC = 4.5 V 3.15 - - V

VCC = 6.0 V 4.2 - - V

VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V

VCC = 4.5 V - - 1.35 V

VCC = 6.0 V - - 1.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−20 µA; VCC = 2.0 V 1.9 - - V

IO=−20 µA; VCC = 4.5 V 4.4 - - V

IO=−20 µA; VCC = 6.0 V 5.9 - - V

IO=−4 mA; VCC = 4.5 V 3.7 - - V

IO=−5.2 mA; VCC = 6.0 V 5.2 - - V

Table 7: Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 03 — 12 November 2004 10 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

12. Dynamic characteristics

VOL LOW-level output voltage VI=V

IH or VIL

IO=20µA; VCC = 2.0 V - - 0.1 V

IO=20µA; VCC = 4.5 V - - 0.1 V

IO=20µA; VCC = 6.0 V - - 0.1 V

IO= 4 mA; VCC = 4.5 V - - 0.4 V

IO= 5.2 mA; VCC = 6.0 V - - 0.4 V

ILI input leakage current VI=V

CC or GND; VCC = 6.0 V - - ±1.0 µA

ICC quiescent supply current VI=V

CC or GND; IO= 0 A; VCC = 6.0 V - - 160 µA

Table 7: Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Table 8: Dynamic characteristics

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 °C

tPHL, tPLH propagation delay CP to TC see Figure 7

VCC = 2.0 V - 96 300 ns

VCC = 4.5 V - 35 60 ns

VCC = 6.0 V - 28 51 ns

VCC = 5.0 V; CL=15pF - 30 - ns

propagation delay TE to TC see Figure 8

VCC = 2.0 V - 50 175 ns

VCC = 4.5 V - 18 35 ns

VCC = 6.0 V - 14 30 ns

propagation delay PL to TC see Figure 9

VCC = 2.0 V - 102 315 ns

VCC = 4.5 V - 37 63 ns

VCC = 6.0 V - 30 53 ns

tPHL propagation delay MR to TC see Figure 9

VCC = 2.0 V - 83 275 ns

VCC = 4.5 V - 30 55 ns

VCC = 6.0 V - 24 47 ns

tTHL, tTLH output transition time see Figure 8

VCC = 2.0 V - 19 75 ns

VCC = 4.5 V - 7 15 ns

VCC = 6.0 V - 6 13 ns

Product data sheet Rev. 03 — 12 November 2004 11 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

tWCP clock pulse width HIGH or

LOW see Figure 7

VCC = 2.0 V 165 22 - ns

VCC = 4.5 V 33 8 - ns

VCC = 6.0 V 28 6 - ns

MR master reset pulse width

LOW see Figure 9

VCC = 2.0 V 125 39 - ns

VCC = 4.5 V 25 14 - ns

VCC = 6.0 V 21 11 - ns

PL preset enable pulse width

LOW see Figure 9

VCC = 2.0 V 125 33 - ns

VCC = 4.5 V 25 12 - ns

VCC = 6.0 V 21 10 - ns

trem removal time MR to CP, PL to CP see Figure 10

VCC = 2.0 V 50 14 - ns

VCC = 4.5 V 10 5 - ns

VCC = 6.0 V 9 4 - ns

tsu set-up time PE to CP see Figure 11

VCC = 2.0 V 75 22 - ns

VCC = 4.5 V 15 8 - ns

VCC = 6.0 V 13 6 - ns

set-up time TE to CP see Figure 12

VCC = 2.0 V 150 44 - ns

VCC = 4.5 V 30 16 - ns

VCC = 6.0 V 26 13 - ns

set-up time Pn to CP see Figure 11

VCC = 2.0 V 75 22 - ns

VCC = 4.5 V 15 8 - ns

VCC = 6.0 V 13 6 - ns

thhold time PE to CP see Figure 11

VCC = 2.0 V 0 −14 - ns

VCC = 4.5 V 0 −5- ns

VCC = 6.0 V 0 −4- ns

hold time TE to CP see Figure 12

VCC = 2.0 V 0 −30 - ns

VCC = 4.5 V 0 −11 - ns

VCC = 6.0 V 0 −9- ns

hold time Pn to CP see Figure 11

VCC = 2.0 V 0 −17 - ns

VCC = 4.5 V 0 −6- ns

VCC = 6.0 V 0 −5- ns

Table 8: Dynamic characteristics

…continued

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 03 — 12 November 2004 12 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

fmax maximum clock frequency see Figure 7

VCC = 2.0 V 3.0 10 - MHz

VCC = 4.5 V 15 29 - MHz

VCC = 6.0 V 18 35 - MHz

VCC = 5.0 V; CL= 15 pF - 32 - MHz

CPD power dissipation capacitance VI= GND to VCC [1] -24-pF

Tamb = −40 °C to +85 °C

tPHL, tPLH propagation delay CP to TC see Figure 7

VCC = 2.0 V - - 375 ns

VCC = 4.5 V - - 75 ns

VCC = 6.0 V - - 64 ns

propagation delay TE to TC see Figure 8

VCC = 2.0 V - - 220 ns

VCC = 4.5 V - - 44 ns

VCC = 6.0 V - - 37 ns

propagation delay PL to TC see Figure 9

VCC = 2.0 V - - 395 ns

VCC = 4.5 V - - 79 ns

VCC = 6.0 V - - 40 ns

tPHL propagation delay MR to TC see Figure 9

VCC = 2.0 V - - 345 ns

VCC = 4.5 V - - 69 ns

VCC = 6.0 V - - 59 ns

tTHL, tTLH output transition time see Figure 8

VCC = 2.0 V - - 95 ns

VCC = 4.5 V - - 19 ns

VCC = 6.0 V - - 16 ns

tWCP clock pulse width HIGH or

LOW see Figure 7

VCC = 2.0 V 205 - - ns

VCC = 4.5 V 41 - - ns

VCC = 6.0 V 35 - - ns

MR master reset pulse width

LOW see Figure 9

VCC = 2.0 V 155 - - ns

VCC = 4.5 V 31 - - ns

VCC = 6.0 V 26 - - ns

PL preset enable pulse width

LOW see Figure 9

VCC = 2.0 V 155 - - ns

VCC = 4.5 V 31 - - ns

VCC = 6.0 V 26 - - ns

Table 8: Dynamic characteristics

…continued

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 03 — 12 November 2004 13 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

trem removal time MR to CP, PL to CP see Figure 10

VCC = 2.0 V 65 - - ns

VCC = 4.5 V 13 - - ns

VCC = 6.0 V 11 - - ns

tsu set-up time PE to CP see Figure 11

VCC = 2.0 V 95 - - ns

VCC = 4.5 V 19 - - ns

VCC = 6.0 V 16 - - ns

set-up time TE to CP see Figure 12

VCC = 2.0 V 190 - - ns

VCC = 4.5 V 38 - - ns

VCC = 6.0 V 33 - - ns

set-up time Pn to CP see Figure 11

VCC = 2.0 V 95 - - ns

VCC = 4.5 V 19 - - ns

VCC = 6.0 V 16 - - ns

thhold time PE to CP see Figure 11

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

hold time TE to CP see Figure 12

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

hold time Pn to CP see Figure 11

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

fmax maximum clock frequency see Figure 7

VCC = 2.0 V 2.4 - - MHz

VCC = 4.5 V 12 - - MHz

VCC = 6.0 V 14 - - MHz

Table 8: Dynamic characteristics

…continued

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 03 — 12 November 2004 14 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Tamb = −40 °C to +125 °C

tPHL/tPLH propagation delay CP to TC see Figure 7

VCC = 2.0 V - - 450 ns

VCC = 4.5 V - - 90 ns

VCC = 6.0 V - - 77 ns

propagation delay TE to TC see Figure 8

VCC = 2.0 V - - 265 ns

VCC = 4.5 V - - 53 ns

VCC = 6.0 V - - 45 ns

propagation delay PL to TC see Figure 9

VCC = 2.0 V - - 475 ns

VCC = 4.5 V - - 95 ns

VCC = 6.0 V - - 81 ns

tPHL propagation delay MR to TC see Figure 9

VCC = 2.0 V - - 415 ns

VCC = 4.5 V - - 83 ns

VCC = 6.0 V - - 71 ns

tTHL/tTLH output transition time see Figure 8

VCC = 2.0 V - - 110 ns

VCC = 4.5 V - - 22 ns

VCC = 6.0 V - - 19 ns

tWCP clock pulse width HIGH or

LOW see Figure 7

VCC = 2.0 V 250 - - ns

VCC = 4.5 V 50 - - ns

VCC = 6.0 V 43 - - ns

MR master reset pulse width

LOW see Figure 9

VCC = 2.0 V 190 - - ns

VCC = 4.5 V 38 - - ns

VCC = 6.0 V 32 - - ns

PL preset enable pulse width

LOW see Figure 9

VCC = 2.0 V 190 - - ns

VCC = 4.5 V 38 - - ns

VCC = 6.0 V 32 - - ns

trem removal time MR to CP, PL to CP see Figure 10

VCC = 2.0 V 75 - - ns

VCC = 4.5 V 15 - - ns

VCC = 6.0 V 13 - - ns

Table 8: Dynamic characteristics

…continued

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 03 — 12 November 2004 15 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

[1] CPD is used to determine the dynamic power dissipation (PD in µW).

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

tsu set-up time PE to CP see Figure 11

VCC = 2.0 V 110 - - ns

VCC = 4.5 V 22 - - ns

VCC = 6.0 V 19 - - ns

set-up time TE to CP see Figure 12

VCC = 2.0 V 225 - - ns

VCC = 4.5 V 45 - - ns

VCC = 6.0 V 38 - - ns

set-up time Pn to CP see Figure 11

VCC = 2.0 V 110 - - ns

VCC = 4.5 V 22 - - ns

VCC = 6.0 V 19 - - ns

thhold time PE to CP see Figure 11

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

hold time TE to CP see Figure 12

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

hold time Pn to CP see Figure 11

VCC = 2.0 V 0 - - ns

VCC = 4.5 V 0 - - ns

VCC = 6.0 V 0 - - ns

fmax maximum clock frequency see Figure 7

VCC = 2.0 V 2.0 - - MHz

VCC = 4.5 V 10 - - MHz

VCC = 6.0 V 12 - - MHz

Table 8: Dynamic characteristics

…continued

GND = 0 V; t

= 6 ns; C

= 50 pF; see Figure 13.

Symbol Parameter Conditions Min Typ Max Unit

7 7 7 7 7 7 7 v 7 7 7 77 7 :7 7:7 7 7

Product data sheet Rev. 03 — 12 November 2004 16 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

13. Waveforms

VM= 0.5 ×VI.V

M= 0.5 ×VI.

Fig 7. Waveforms showing the clock input (CP) to

TC propagation delays, the clock pulse width,

the output transition times and the maximum

clock pulse frequency

Fig 8. Waveforms showing the TE to TC propagation

delays

001aab926

CP input

TC output

tPHL

tTHL tTLH

tPLH

1/fmax

001aab927

TE input

TC output

tPHL

tTHL tTLH

tPLH

VM= 0.5 ×VI.V

M= 0.5 ×VI.

Fig 9. Waveforms showing PL, MR,PntoTC

propagation delays Fig 10. Waveforms showing removal time for MR and

001aab928

Pn, PL, MR

input

TC output

tPHL tPLH

001aab929

PL, MR

input

CP input

trem

ﬂ

Product data sheet Rev. 03 — 12 November 2004 17 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

VM= 0.5 ×VI.

Fig 11. Waveforms showing hold and set-up times for

Pn, PE to CP Fig 12. Waveforms showing hold and set-up times for

MR or PE to CP

VMstable

001aab931

PE input

CP input

P0 to P7

input

tsu th

001aab930

TE or PE

input

CP input

tsu th

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 13. Load circuitry for switching times

Table 9: Test data

Supply Input Load

VCC VItr, tfCL

2.0 V VCC 6 ns 50 pF

4.5 V VCC 6 ns 50 pF

6.0 V VCC 6 ns 50 pF

5.0 V VCC 6 ns 15 pF

mna101

VCC

VIVO

RTCL

PULSE

GENERATOR D.U.T.

Product data sheet Rev. 03 — 12 November 2004 18 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

14. Application information

Fig 14. Programmable timer

Fig 15. Divide-by-N counter

001aab932

VCC

10kΩ

time-out

start

GND

40103

VCC

fIN

001aab933

GND

40103

VCC

fOUT =

fIN

N + 1

F1 Ha ﬂ ﬂ}ﬁ»Heﬁw»H 79‘ ,,,,,, +1 ,,,,,,, ,, \ LJLLJKJJAJJiLLr'LUJAJJhJ

Product data sheet Rev. 03 — 12 November 2004 19 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

15. Package outline

Fig 16. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

f% i ’\ FHHHHHHHH ,—;— GHEPHLHHHH +D +

Product data sheet Rev. 03 — 12 November 2004 20 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Fig 17. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014

0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

SQ 99443—27»

Product data sheet Rev. 03 — 12 November 2004 21 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Fig 18. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

G‘HHH1HHHF

Product data sheet Rev. 03 — 12 November 2004 22 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Fig 19. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 12 November 2004 23 of 25

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

16. Revision history

Table 10: Revision history

Document ID Release

date Data sheet status Change

notice Doc. number Supersedes

74HC40103_3 20041112 Product data sheet - 9397 750 13812 74HC_HCT40103_CNV_2

Modifications: •The format of this data sheet has been redesigned to comply with the current presentation

and information standard of Philips Semiconductors.

•Removed type number 74HCT40103.

•Inserted family specification.

74HC_HCT40103_CNV_2 19970918 Product specification - - 74HC_HCT40103_1

74HC_HCT40103_1 19901201 Product specification - - -

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

Product data sheet Rev. 03 — 12 November 2004 24 of 25

17. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18. Definitions

Short-form specification — The data in a short-form specification is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

specification is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the specified use without further testing or modification.

19. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

specified.

20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level Data sheet status[1] Product status [2] [3] Definition

I Objective data Development This data sheet contains data from the objective specification for product development. Philips

Semiconductors reserves the right to change the specification in any manner without notice.

II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 12 November 2004

Document number: 9397 750 13812

Published in The Netherlands

Philips Semiconductors 74HC40103

8-bit synchronous binary down counter

21. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3

6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Functional description . . . . . . . . . . . . . . . . . . . 7

8.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

10 Recommended operating conditions. . . . . . . . 8

11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 10

13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Application information. . . . . . . . . . . . . . . . . . 18

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23

17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 24

18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

19 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

20 Contact information . . . . . . . . . . . . . . . . . . . . 24

74HC40103 Datasheet by NXP USA Inc.

INFORMATION

HELP

CONTACT US

FOLLOW US