Details, datasheet, quote on part number: 74F382
| Part | 74F382 |
| Category | Logic => Arithmetic Functions |
| Title | Bipolar->F Family |
| Description | 4-Bit Arithmetic Logic Unit |
| Company | Fairchild Semiconductor |
| Datasheet | Download 74F382 Datasheet |
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| Quote |
| Features, Applications |
The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet. Featuress Performs six arithmetic and logic functions s Selectable LOW (clear) and HIGH (preset) functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic Order Number 74F382SJ 74F382PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pin Names + 4 OVR F0�F3 Description A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL �A/-3.0 mA Signals applied to the Select inputs S0�S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the Exclusive-OR + 3 and 4; a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure 1. Operation Clear B Minus A Minus B A Plus B AB A+B AB PresetInputs Function CLEAR B MINUS L Cn MINUS PLUS AB A+B AB PRESET |
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