The F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.

s Encodes eight data lines in priority s Provides 3-bit binary priority code s Input enable capability s Signals when data is present on any input s Cascadable for priority encoding of n bits

Order Number 74F148SJ 74F148PC Package Number M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

U.L. Pin Names GS A0�A2 Description HIGH/LOW Priority Input (Active LOW) Priority Inputs (Active LOW) Enable Input (Active LOW) Enable Output (Active LOW) Group Signal Output (Active LOW) Address Outputs (Active LOW) Input IIH/IIL Output IOH/IOL �A/-0.6 mA

The F148 8-input priority encoder accepts data from eight active LOW inputs (I0�I7) and provides a binary representation on the three active LOW outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line 7 having the highest priority. A HIGH on the Enable Input (EI) will force all outputs to the inactive (HIGH) state and allow new data to settle without producing erroneous information at the outputs.A Group Signal output (GS) and Enable Output (EO) are provided along with the three priority data outputs GS is active LOW when any input is LOW: this indicates when any input is active. EO is active LOW when all inputs are HIGH. Using the Enable Output along with the Enable Input allows cascading for priority encoding on any number of input signals. Both EO and GS are in the inactive HIGH state when the Enable Input is HIGH.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output High Leakage Current Input Leakage Test Output Leakage Circuit Current IIL IOS ICCH ICCL Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current VCC 5% VCC 10% VCC Min 0.8 -1.2 Typ Max Units �A mA Min Max 0.0 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -1 mA IOL 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID 1.9 �A All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN 0.5V (I0, EI) VIN 0.5V (I1�I7) VOUT VO = HIGH VO = LOW