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74ALVCH16841 Datasheet by NXP USA Inc.
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PHILIPS
74ALVCH16841
20-bit bus interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Jul 27
INTEGRATED CIRCUITS
PIN CONFIGURATION
\
1—HT
LHJLILHJLHJLHJLHJLHJUUUUUUUUUUUUUUU
flflflflflflflflflflflflflflflflflflflflflflflflflfl
Power dwssupauon capamlance er bufler v- = GND to v~~'
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
2
1998 Jul 27 853-2093 19785
FEATURES
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Wide supply voltage range of 1.2V to 3.6V
•CMOS low power consumption
•Direct interface with TTL levels
•MULTIBYTETM flow-through standard pin-out architecture
•Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
•Current drive ±24 mA at 3.0 V
•All inputs have bus hold circuitry
•Output drive capability 50Ω transmission lines @ 85°C
•3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.
When nOE is LOW, the data in the registers appears at the outputs.
When nOE is High the outputs are in High-impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q2
1Q9
VCC
2Q3
VCC
2Q1
2Q4
2Q8
2OE
2Q7
1LE
1D0
1D1
GND
1D2
1D3
1D4
1D5
2D0
1D6
1D7
2D1
2D2
GND
2D4
VCC
2D5
VCC
2D3
2D6
GND
2D8
2LE
2D7
SA00076
2Q0
GND
2Q5
28
27
26
25
49
50
51
52
53
54
55
56
2D9
1D9
1D8
GND
2Q9
GND
2Q6
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
nDn to nQn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF 2.5
2.4 ns
tPHL/tPLH Propagation delay
nLE to nQn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF 2.5
2.4 ns
CIInput capacitance 5.0 pF
CPD
Power dissi
p
ation ca
p
acitance
p
er buffer
VI= GND to VCC1
Outputs enabled 19 p
F
C
PD
Power
dissi ation
ca acitance
er
buffer
V
I =
GND
to
V
CC
1
Outputs disabled 3
F
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C74ALVCH16841 DGG ACH16841 DGG SOT364-1
LOGIC SYMBOL (lEEE/IEC)
LOGIC SYMBOL
LOGIC DIAGRAM
L
ALO
,W
L I
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27 3
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 1OE Output enable inputs
(active-LOW)
56 1LE Latch enable inputs
(active HIGH)
55, 54, 52, 51, 49,
48, 47, 45, 44, 43 1D0 – 1D9 Data inputs
2, 3, 5, 6, 8, 9, 10,
12, 13, 14 1Q0 – 1Q9 Data outputs
4, 11, 18, 25, 32,
39, 46, 53 GND Ground (0V)
7, 22, 35, 50 VCC Positive supply
voltage
28 2OE Output enable inputs
(active-LOW)
29 2LE Latch enable inputs
(active HIGH)
42, 41, 40, 38, 37,
36, 34, 33, 31, 30 2D0 – 2D9 Data inputs
15, 16, 17, 19, 20,
21, 23, 24, 26, 27 2Q0 – 2Q9 Data outputs
FUNCTION TABLE
INPUTS OUTPUT
nOE LE Dx Q
L H L L
L H H H
L L X Q0
H X X Z
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
LOGIC SYMBOL
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D8 1D9
1Q8 1Q9
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D8 2D9
2Q8 2Q9
55 54 52 51 49 48 47 45 44 43
56
1
29
28
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
15 16 17 19 20 21 23 24 26 27
SH00023
1LE
1OE
2LE
2OE
LOGIC SYMBOL (IEEE/IEC)
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1D8
1D9
1Q8
1Q9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2D8
2D9
2Q8
2Q9
EN4
2 ∇
EN2
4 ∇
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1D
3D
C1
C3
1OE
1LE
2OE
2LE
SH00152
LOGIC DIAGRAM
nD0
nQ0
D
LE
nLE
nOE
SH00151
f
PET
DC mpul voltage
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27 4
BUS HOLD CIRCUIT
To internal circuit
VCC
Data Input
SW00044
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
VCC
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load) 2.3 2.7
V
V
CC DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load) 3.0 3.6
V
VIDC Input voltage range 0 VCC V
VODC output voltage range 0 VCC V
Tamb Operating free-air temperature range –40 +85 °C
tr, tfInput rise and fall times VCC = 2.3 to 3.0V
VCC = 3.0 to 3.6V 0
020
10 ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
IIK DC input diode current VI 0 –50 mA
VI
DC in
p
ut voltage
For control pins1–0.5 to +4.6
V
V
I
DC
in ut
voltage
For data inputs1–0.5 to VCC +0.5
V
IOK DC output diode current VO VCC or VO 0 50 mA
VODC output voltage Note 1 –0.5 to VCC +0.5 V
IODC output source or sink current VO = 0 to VCC 50 mA
IGND, ICC DC VCC or GND current 100 mA
Tstg Storage temperature range –65 to +150 °C
PTOT
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K 850
600 mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
LOW le"e1 Inp‘ « vonage
*23t03.6V‘V=V UFV Ii IOOuA
men-v \e-el amp"! Wattage
723mm V:V orV baoouA
23m 3.6V
: V “’GND
Bus mm LOW sustammg currem
Bus mm HIGH susiammg cutrenl
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27 5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
HIGH level In
p
ut voltage
VCC = 2.3 to 2.7V 1.7 1.2
V
V
IH
HIGH
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 2.0 1.5
V
V
LOW level In
p
ut voltage
VCC = 2.3 to 2.7V 1.2 0.7
V
V
IL
LOW
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 1.5 0.8
V
VCC =23to36V
;
V=V or V
;
IO= 100µA
VCC 02
VCC
V
CC =
2
.
3
to
3
.
6V
;
V
I =
V
IH
or
V
IL;
I
O = –
100
µ
A
V
CC
0
.
2
V
CC
VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC0.3 VCC0.08
VO
HIGH level out
p
ut voltage
VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.26
V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC0.14
V
VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.09
VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC0.28
V=23to36V
;
V=V or V
;
I = 100µA
GND
020
V
V
CC =
2
.
3
to
3
.
6V
;
V
I =
V
IH
or
V
IL;
I
O =
100
µ
A
GND
0
.
20
V
VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V
VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70
VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 V
VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55
VCC =23to36V
;
IIInput leakage current
V
CC =
2
.
3
to
3
.
6V
;
V V or GND
0.1 5
µ
A
I
g
V
I =
V
CC or
GND
µ
IOZ 3-State output OFF-state current VCC = 2.3 to 3.6V; VI = VIH or VIL;
VO = VCC or GND 0.1 10 µA
ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA
∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA
IBHL2
Bus hold LOW sustaining current
VCC = 2.3V; VI = 0.7V 45 –
µA
I
BHL
2
Bus
hold
LOW
sustaining
current
VCC = 3.0V; VI = 0.8V 75 150
µA
IBHH2
Bus hold HIGH sustaining current
VCC = 2.3V; VI = 1.7V –45
µA
I
BHH
2
Bus
hold
HIGH
sustaining
current
VCC = 3.0V; VI = 2.0V –75 –175
µA
IBHLO2Bus hold LOW overdrive current VCC = 3.6V 500 µA
IBHHO2Bus hold HIGH overdrive current VCC = 3.6V –500 µA
NOTES:
1. All typical values are at Tamb = 25°C.
2. Valid for data inputs of bus hold parts.
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27 6
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 2.3 to 2.7V UNIT
MIN TYP1MAX
tPLH/tPHL Propagation delay
nDn to nQn1, 5 1.0 2.5 5.0 ns
tPLH/tPHL Propagation delay
nLE to nQn2, 5 1.0 2.5 5.6 ns
tPZH/tPZL 3-State output enable time
nOEn to nQn4, 5 1.0 2.7 6.2 ns
tPHZ/tPLZ 3-State output disable time
nOEn to nQn4, 5 1.1 2.2 5.3 ns
tWnLE pulse width HIGH 2, 5 3.3 1.5 – ns
tSU Set up time nDn to nLE 3, 5 1.3 0.1 – ns
ThHold time nDn to nLE 3, 5 1.4 0.3 – ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF
LIMITS LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3 ± 0.3V VCC = 2.7V UNIT
MIN TYP1, 2MAX MIN TYP1MAX
tPLH/tPHL Propagation delay
nDn to nQn1, 5 1.0 2.4 3.9 1.0 2.6 4.7 ns
tPLH/tPHL Propagation delay
nLE to nQn2, 5 1.0 2.4 4.3 1.0 2.6 5.1 ns
tPZH/tPZL 3-State output enable time
nOEn to nQn4, 5 1.0 2.3 4.9 1.0 3.1 6.0 ns
tPHZ/tPLZ 3-State output disable time
nOEn to nQn4, 5 1.3 2.9 4.1 1.3 3.1 4.3 ns
tWnLE pulse width HIGH 2, 5 3.3 1.5 – 3.3 1.5 – ns
tSU Set up time nDn to nLE 3, 5 1.0 0.6 – 1.1 0.1 – ns
thHold time nDn to nLE 3, 5 1.4 0.2 – 1.7 0.2 – ns
NOTES:
1. All typical values are measured Tamb = 25°C.
2. Typical value is measured at VCC = 3.3V
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
1998 Jul 27 7
AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND
VCC < 2.3V RANGE
VM = 0.5 VCC
VX = VOL + 0.15V
VY = VOH –0.15V
VOL and VOH are the typical output voltage drop that occur with the
output load.
AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND
VCC = 2.7V RANGE
VM = 1.5 V
VX = VOL + 0.3V
VY = VOH –0.3V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = 2.7V
VI = VCC
Dn
INPUT
tPHL tPLH
VOL
VI
GND
VOH
Qn
OUTPUT
VM
VM
SH00153
Waveform 1. The input (Dn) to output (Qn) propagation delay
LE INPUT
Qn OUTPUT
VI
GND
VOH
VOL
tPHL tPLH
tW
VM
VM
VM
SH00150
Waveform 2. The latch enable (LE) pulse width, the latch enable
input to output (Qn) propagation delay
Dn
INPUT
LE
INPUT
tSU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
tSU
th
VI
GND
VI
GND
VM
VM
SH00149
Waveform 3. The data set up and hold times for the Dn input to
the LE input
tPLZ tPZL
VI
nOE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND outputs
enabled outputs
enabled
outputs
disabled
tPHZ
VM
VM
VM
tPZH
VX
VY
SH00137
Waveform 4. 3-State enable and disable times
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
VCC
RL = 500 Ω
Test Circuit for switching times
Open
GND
S1
DEFINITIONS
VCC VI
< 2.7V VCC
TEST S1
tPLH/tPHL Open
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
2 VCC
tPLZ/tPZL 2.7V2.7–3.6V
tPHZ/tPZH GND
RL = 500 Ω
2 * VCC
SV00906
Waveform 5. Load circuitry for switching times
+2
4HHHHHHHHHHHHF
0
f (M A
p1n1index \1 1
79
El “P
DIMENSIONS (mm nreihe orlqlnnl dime-Mona).
A
mm A1 A2 A: 0,, c D") E‘a e v z e
015 105 023 0.2 141 5'2 05 a“
‘2 005 035 025 017 0.1 139 6,0 0‘5 0" 01 0”
1. Plasma or mam pvolmsmns 010.15 mm max‘mum per we are nollncluded.
2. Plasuc .meneau protrusions of 0.25 mm maxumum pet mm are not momded
gqumE REFERENCES
ISSUEDATE
VERSW" E1: JEDEC EIAJ
semen-1 MO-IEGEE m
Philips Semiconductors Product specification
74ALVCH16841
20-bit bus interface D-type latch (3-State)
1998 Jul 27 8
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
Philips Semiconductors Product specification
74ALVCH16841
20-bit bus interface D-type latch (3-State)
1998 Jul 27 9
NOTES
Dommentmdernumber 93977750704551
Laémnwbm
PH I LI PS
Philips Semiconductors Product specification
74ALVCH16841
20-bit bus interface D-type latch (3-State)
1998 Jul 27 10
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 07-98
Document order number: 9397-750-04561
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
