74ALVCH16841 Datasheet by Nexperia USA Inc.

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74ALVCH16841

20-bit bus interface D-type latch; 3-state

Rev. 3 — 12 September 2018 Product data sheet

1. General description

The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch

and 3-state outputs for bus oriented applications. The two sections of each register are controlled

independently by the latch enable (nLE) and output enable (nOE) control gates.

When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the

outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of

the flip-flops.

The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating

data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down

resistors.

2. Features and benefits

•Wide supply voltage range of 1.2 V to 3.6 V

•CMOS low power consumption

•Direct interface with TTL levels

•Current drive ±24 mA at VCC = 3.0 V

•MULTIBYTE flow-through standard pin-out architecture

•Low inductance multiple VCC and GND pins for minimize noise and ground bounce

•All data inputs have bushold

•Output drive capability 50 Ω transmission lines at 85 °C

•3-state non-inverting outputs for bus oriented applications

•Complies with JEDEC standards:

•JESD8-5 (2.3 V to 2.7 V)

•JESD8B/JESD36 (2.7 V to 3.6 V)

•ESD protection:

•HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

•CDM JESD22-C101E exceeds 1000 V

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74ALVCH16841DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

74ALVCH16841 IOE 20E 55 i i 2 54 3 52 5 51 s 49 B 43 9 47 1a 45 12 44 13 43 14 41 16 4a 17 3a 19 37 20 3e 21 34 23 33 24 31 26 3a 27 1LE 2LE 723 55 52 51 49 47 45 43 42 41 4D 33 37 35 33 31 an mmmmm 12 14 15 15 17 19 2o 21 23 24 25 27 100 101 102 103 104 105 106 107 103 109 200 201 202 203 204 205 206 207 203 209 ass-029041 W % 2ﬁ<>°7 200 “3.029042 If T $ 3% T Irv/15004

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

4. Functional diagram

aaa-029040

13 1Q8

14 1Q9

15 2Q0

16 2Q1

17 2Q2

19 2Q3

20 2Q4

21 2Q5

56 29

1 28

23 2Q6

24 2Q7

26 2Q8

27 2Q9

21Q0

31Q1

51Q2

61Q3

81Q4

91Q5

10 1Q6

12 1Q7

1D8

1D9

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D9

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7 45

1LE 2LE

1OE 2OE

Fig. 1. Logic symbol

1D 2

1EN2

EN4

aaa-029041

13 1Q8

14 1Q9

15 2Q0

16 2Q1

17 2Q2

19 2Q3

20 2Q4

21 2Q5

23 2Q6

24 2Q7

26 2Q8

27 2Q9

21Q0

3D 4

31Q1

51Q2

61Q3

81Q4

91Q5

10 1Q6

12 1Q7

1D8

1D9

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D9

1D0

2LE

2OE

1LE

1OE

1D1

1D2

1D3

1D4

1D5

1D6

1D7 45

Fig. 2. IEC logic symbol

aaa-029042

to 9 other channels

LATCH

1LE

1D0 1Q0

1OE

to 9 other channels

LATCH

2LE

2D0 2Q0

2OE

Fig. 3. Logic diagram

to internal circuit

mna004

VCC

data

input

Fig. 4. Bushold circuit

Product data sheet Rev. 3 — 12 September 2018 2 / 12

74ALVCH16841 74ALVCH16341 D D D D j:jjjjjjjjjjjjjjjjjjjjjjjjjj O EECEEEEEEEEEEEEEEEEEEEEEEEEE in in ass—mm Table 2. Pin description 16E ZUE

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

5. Pinning information

5.1. Pinning

74ALVCH16841

1LE

1D0

1D1

GND

1D2

1D3

VCC

1D4

1D5

1D6

GND

1D7

1D8

1D9

2D0

2D1

2D2

GND

2D3

2D4

2D5

VCC

2D6

2D7

GND

2D8

2D9

2LE

aaa-029043

1OE

1Q0

1Q1

GND

1Q2

1Q3

VCC

1Q4

1Q5

1Q6

GND

1Q7

1Q8

1Q9

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

VCC

2Q6

2Q7

GND

2Q8

2Q9

2OE

Fig. 5. Pin configuration SOT364-1 (TSSOP56)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8, 1D9 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data input

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8, 2D9 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data input

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8, 1Q9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 data output

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8, 2Q9 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data output

1OE, 2OE 1, 28 output enable inputs

(active-LOW)

1LE, 2LE 56, 29 latch enable inputs

GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V)

VCC 7, 22, 35, 50 supply voltage

Product data sheet Rev. 3 — 12 September 2018 3 / 12

74ALVCH16841 nUE Table 5. Recommended operating conditions

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Inputs Outputs

nOE nLE nDn nQn

L H L L

L H H H

L L X Q0

H X X Z

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +4.6 V

For control pins [1] -0.5 +4.6 VVIinput voltage

For data inputs [1] -0.5 VCC + 0.5 V

VOoutput voltage [1] -0.5 VCC + 0.5 V

IIK input clamping current VI < 0 V -50 - mA

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

IOoutput current VO = 0 V to VCC - ±50 mA

ICC supply current - 100 mA

IGND ground current -100 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +85 °C [2] - 600 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

for maximum speed performance; 30 pF output load 2.3 2.7 VVCC supply voltage

for maximum speed performance; 50 pF output load 3.0 3.6 V

VIinput voltage 0 VCC V

VOoutput voltage 0 VCC V

Tamb ambient temperature in free air -40 +85 °C

VCC = 2.3 V to 3.0 V - 20 ns/VΔt/ΔV input transition rise and fall rate

VCC = 3.0 V to 3.6 V - 10 ns/V

Product data sheet Rev. 3 — 12 September 2018 4 / 12

74ALVCH16841

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C

Symbol Parameter Conditions Min Typ[1] Max Unit

VCC = 2.3 V to 2.7 V 1.7 1.2 - VVIH HIGH-level

input voltage VCC = 2.7 V to 3.6 V 2.0 1.5 - V

VCC = 2.3 V to 2.7 V - 1.2 0.7 VVIL LOW-level

input voltage VCC = 2.7 V to 3.6 V - 1.5 0.8 V

VI = VIH or VIL

IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V

IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V

IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V

IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V

IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V

VOH HIGH-level

output voltage

IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V

VI = VIH or VIL

IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V

IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V

IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V

IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V

VOL LOW-level

output voltage

IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V

IIinput

leakage current

VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA

IOZ OFF-state

output current

VCC = 2.3 V to 3.6 V; VI = VIH or VIL;

VO = VCC or GND

- 0.1 10 μA

ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND;

IO = 0 A

- 0.2 40 μA

ΔICC additional

supply current

VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V;

IO = 0 A

- 150 750 μA

VCC = 2.3 V; VI = 0.7 V 45 - - μAIBHL bus hold LOW

current VCC = 3.0 V; VI = 0.8 V 75 150 - μA

VCC = 2.3 V; VI = 1.7 V -45 - - μAIBHH bus hold HIGH

current VCC = 3.0 V; VI = 2.0 V -75 -175 - μA

IBHLO bus hold LOW

overdrive current

VCC = 3.6 V 500 - - μA

IBHHO bus hold HIGH

overdrive current

VCC = 3.6 V -500 - - μA

CIinput capacitance - 5.0 - pF

[1] All typical values are measured at Tamb = 25 °C.

Product data sheet Rev. 3 — 12 September 2018 5 / 12

74ALVCH16841 Fig. 10

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10;

Tamb = -40 °C to +85 °C

Symbol Parameter Conditions Min Typ[1] Max Unit

nDn to nQn; see Fig. 6 [2]

VCC = 2.3 V to 2.7 V 1.0 2.5 5.0 ns

VCC = 2.7 V 1.0 2.6 4.7 ns

VCC = 3.0 V to 3.6 V 1.0 2.4 3.9 ns

nLE to nQn; see Fig. 7

VCC = 2.3 V to 2.7 V 1.0 2.5 5.6 ns

VCC = 2.7 V 1.0 2.6 5.1 ns

tpd propagation delay

VCC = 3.0 V to 3.6 V 1.0 2.4 4.3 ns

nOE to nQn; see Fig. 9 [3]

VCC = 2.3 V to 2.7 V 1.0 2.7 6.2 ns

VCC = 2.7 V 1.0 3.1 6.0 ns

ten enable time

VCC = 3.0 V to 3.6 V 1.0 2.3 4.9 ns

nOE to nQn; see Fig. 9 [4]

VCC = 2.3 V to 2.7 V 1.1 2.2 5.3 ns

VCC = 2.7 V 1.3 3.1 4.3 ns

tdis disable time

VCC = 3.0 V to 3.6 V 1.3 2.9 4.1 ns

nDn to nLE; see Fig. 8

VCC = 2.3 V to 2.7 V 1.3 0.1 - ns

VCC = 2.7 V 1.1 0.1 - ns

tsu set-up time

VCC = 3.0 V to 3.6 V 1.0 0.6 - ns

nDn to nLE; see Fig. 8

VCC = 2.3 V to 2.7 V 1.4 0.3 - ns

VCC = 2.7 V 1.7 0.2 - ns

thhold time

VCC = 3.0 V to 3.6 V 1.4 0.2 - ns

tWpulse width nLE HIGH; VCC = 2.3 V to 3.6 V; see Fig. 7 3.3 1.5 - ns

per latch; VI = GND to VCC [5]

outputs enabled - 19 - pF

CPD power dissipation

capacitance

outputs disabled - 3 - pF

[1] Typical values are measured at Tamb = 25 °C

Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V.

Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V.

[2] tpd is the same as tPLH and tPHL.

[3] ten is the same as tPZL and tPZH.

[4] tdis is the same as tPLZ and tPHZ.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC

2 × fi × N + ∑ (CL × VCC

2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

∑(CL × VCC

2 × fo) = sum of outputs.

Product data sheet Rev. 3 — 12 September 2018 6 / 12

74ALVCH16841 summon 7 DDTuamDH Table 8 Table 8 v Oman/"013 Table 8 v Table 8 00155/795

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

10.1. Waveforms and test circuit

001aam011

nDn input

nQn output

tPHL tPLH

GND

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that

occur with the output load.

Fig. 6. Input (nDn) to output (nQn) propagation delays

001aam012

tPHL

VMVMVM

GND

VOH

VOL

nLE input

nQn output

tPLH

VMVM

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that

occur with the output load.

Fig. 7. Latch enable input (nLE) to data output (nQn)

propagation delays and pulse width (nLE)

001aam013

GND

nDn input

nLE input

tsu

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 8. Data setup and hold times for input (nDn) to input (nLE)

001aal795

tPLZ

tPHZ

outputs

disabled

outputs

enabled

outputs

enabled

nQn output

LOW-to-OFF

OFF-to-LOW

nQn output

HIGH-to-OFF

OFF-to-HIGH

nOE input

VOL

VOH

VCC

VMVM

GND

tPZL

tPZH

Measurement points are given in Table 8.

VOL and VOH are typical output levels that occur with the output load.

Fig. 9. 3-State enable and disable times

Product data sheet Rev. 3 — 12 September 2018 7 / 12

74ALVCH16841 Table 8. Measurement points mamas Table 9 Table 9. Test data

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

Table 8. Measurement points

Input Output

VCC VIVMVMVxVy

< 2.3 V VCC 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V

2.3 V to 2.7 V VCC 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V

2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

VEXT

VCC

VIVO

001aae235

DUT

PULSE

GENERATOR

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator;

VEXT = External voltage for measuring switching times.

Fig. 10. Test circuit for measuring switching times

Table 9. Test data

Input Load VEXT

VCC VItr, tfRLCLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL

< 2.3 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open

2.3 V to 2.7 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open

2.7 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open

Product data sheet Rev. 3 — 12 September 2018 8 / 12

74ALVCH16841 TSSOPSG: plastic lhin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

11. Package outline

UNIT A

1 A

2 A

3 b

p c D

(1) E

(2) e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.2

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT364-1 99-12-27

03-02-19

w M

detail X

(A )

0.25

1 28

56 29

pin 1 index

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0 0.5 1

8.3

7.9

0.50

0.35

0.5

0.1

0.08 0.25

0.8

0.4

E v M A

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

max.

1.2

5 mm

scale

MO-153

Fig. 11. Package outline SOT364-1 (TSSOP56)

Product data sheet Rev. 3 — 12 September 2018 9 / 12

74ALVCH16841 Table 10. Abbreviations Table 11. Revision history

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74ALVCH16841 v.3 20180912 Product data sheet - 74ALVCH16841 v.2

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

74ALVCH16841 v.2 19980727 Product specification - 74ALVCH16841 v.1

74ALVCH16841 v.1 19980727 Product specification -

Product data sheet Rev. 3 — 12 September 2018 10 / 12

74ALVCH16841 same In a deswgn on new sheet’ .5 exp‘amed in status er den/ms) described 2 «ms documenl was publish es. The latest produd slam hugs waw nexg mm sale 7 Max us or eon ns Mcomme m me genera‘ ierm and can m llwww nex er

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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the Absolute Maximum Ratings System of IEC 60134) will cause permanent

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states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 3 — 12 September 2018 11 / 12

74ALVCH16841

Nexperia 74ALVCH16841

20-bit bus interface D-type latch; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description............................................................. 3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................4

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 7

11. Package outline.......................................................... 9

12. Abbreviations............................................................ 10

13. Revision history........................................................10

14. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 12 September 2018

Product data sheet Rev. 3 — 12 September 2018 12 / 12

74ALVCH16841 Datasheet by Nexperia USA Inc.

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