Counter inputs ENT, ENP and output RCO

Question

I am using an IC 74162 (decimal counter) and I know that both enable inputs ENT and ENP must be on so that the counter works, but I am not sure about the difference between them, and their relation with the output RCO.

Thank you!

Answer 1

A 74162 is a decimal counter.

The EN inputs and the RCO outputs work as follows.

In order to respond to a rising clock edge by counting, ENT, ENP, LD and MR must all be high.

If this is true, on a count of 9 the RCO output will go high. Ordinarily, you tie ENP, LD and MR high, then connect the RCO of one counter to the ENT of the next counter in the chain, and so on.

So, for the first counter, at a count of 9 RCO will go high and feed ENT of the next. A rising clock edge will then cause the first counter to go to 0 and the next counter to count 1 step (increment). RCO of the second counter will go high when the output is 99, so this can be used to enable a third counter, which will then count hundreds. And so on.

The difference between ENT and ENP is that ENP enables the counter but does not affect RCO. So it enables the counters but does not affect the transition count.

You'll notice (I hope) that for a chain of 162s all the clocks must be tied together. As opposed to something like a 7490, all counters will switch at exactly the same time, as opposed to a 7490 which switch in a ripple fashion (which is why it is called a ripple counter). This allows, among other things, much easier feedback by decoding the counter outputs, since they all change at the same time and you don't get the "skew delays" which plague ripple counters. So in order to make a counter do something other than simple divide by 10 counting, you can make a counter which will recycle on any count you like.

Let's take a 2-stage counter, and try to make a divide by 79. You can feed back the output to the MR input to do this, but you need to do in on an output of 78, not 79, since the MR will reset the counter to 0 rather than 1. So you use a 4 input NAND gate which looks at Q0, Q1 and Q2 of the second counter (seven, right?) and Q3 of the first counter (8), and connect the NAND to the MR of both counters.

At a count of 78 the output of the NAND will go low, and on the next clock the counter chain will reset to 0, and the cycle will repeat indefinitely. But note that you can only do this with 74162 and 74163, not 74160 and 74161. The difference can be found on the data sheets: the 160 and 161 have asynchronous resets. while the 162 and 163 have synchronous resets. This means that if MR goes low the 160 and 161 will reset immediately (even for a brief spike) while the 162 and 163 will only respond on the clock edge.

Also note that in all 4 chips the LD input is synchronous.

I suggest you look closely at the data sheets for the ICs involved. They will have timing diagrams which explain all this.