x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply 3.3V (�5%) I/O Supply (VDDQ) Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA)

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMs organized x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be

it read or write. The IDT71V3557/59 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/ LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after chip is deselected or a write is initiated. The IDT71V3557/59 have an on-chip burst counter. In the burst mode, the IDT71V3557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71V3557/59 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 20mm 100-pin thin plastic quad flatpack (TQFP) as well a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

Input Output Input I/O Supply Synchronous Asynchronous Synchronous N/A Synchronous Static Synchronous N/A Synchronous Asynchronous Synchronous Static

CE2 OE R/W CEN BW3, BW4 CLK ADV/LD LBO TMS TDI TCK TDO TRST I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS Address Inputs Chip Enables Output Enable Read/Write Signal Clock Enable Individual Byte Write Selects Clock Advance burst address / Load new address Linear / Interleaved Burst Order Test Mode Select Test Data Input Test Clock Test Data Output JTAG Reset (Optional) Sleep Mode Data Input / Output Core Power, I/O Power Ground

18, 3.3V Synchronous SRAMs with ZBTTM Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Symbol A0-A17 ADV/LD Pin Function Address Inputs Advance / Load I/O I Active N/A Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD is a synchronous input that is used to load the internal registers with new addre ss and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high. R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Synchronous active low chip enable. CE1 and CE2 are used with 2 to enable the or CE2 sampled high CE 2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE 2 has inverted polarity but otherwise identical to CE1 and CE2. This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data output path is flow-through (no output register). Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation.. Asynchronous output enable. OE must be low to read data from the 71V3557/59. When OE is HIGH the I/O pins are in a high-impedance state. OE d oes not need to be actively controlled for re ad and write cycles. In normal operation, OE can be tied low. Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP controller. Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. This pin has an internal pullup. Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown. 3.3V core power supply. 3.3V I/O Supply. Ground.

18, 3.3V Synchronous SRAMs with ZBTTM Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges