The is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Outputs source/sink 24 mA See '273 for reset version See '377 for clock enable version See '373 for transparent latch version See '574 for broadside pinout version See '564 for broadside pinout version with inverted outputs n 'ACT374 has TTL-compatible inputs n Standard Military Drawing (SMD) 'ACT374: 5962-87631

n ICC and IOZ reduced 50% n Buffered positive edge-triggered clock n TRI-STATE outputs for bus-oriented applications

TRI-STATE is a registered trademark of National Semiconductor Corporation. FACT is a registered trademark of Fairchild Semiconductor Corporation.

The 'AC/'ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP -0.5V to VCC -0.5V to VCC + 0.5V

Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from to 2.0V VCC 0V to VCC 0V to VCC to +125�C

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT � circuits outside databook specifications.

Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) to +125�C Guaranteed Limits (Note 2) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage (Note 2) VIN = VIL or VIH 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum TRI-STATE Current V �A IOL VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND mA V IOUT �A V IOH mA V IOUT �A V VOUT 0.1V or VCC 0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions