COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
28
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CSA
ORA
W/RA
MBA
ENA
A0-A35
CLKA
IRB
CLKB
CSB
4677 drw23
W/RB
B0-B35
MBB
ENB
12
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
WFF
t
WFF
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
FIFO2 FULL
LOW
LOW
LOW
HIGH
LOW
LOW
(1)
Write
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
29
Figure 22.
FFBFFB
FFBFFB
FFB
Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.
CSA
EFA
MBA
ENA
A0-A35
CLKA
FFB
CLKB
CSB
4677 drw24
W/RB
12
B0-B35
MBB
ENB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
LOW
LOW
(1)
FIFO2 Full
t
WFF
t
WFF
Write
COMMERCIAL TEMPERATURE RANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
30
Figure 25. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
Figure 23. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 24. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104.
4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
AEB
CLKA
ENB
4677 drw25
ENA
CLKB
2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
X1 Words in FIFO1
(X1+1) Words in FIFO1
(1)
AEA
CLKB
ENA
4677 drw26
ENB
CLKA
2
1
tENS2
tENH
tSKEW2
tPAE
tPAE
tENS2
tENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
AFA
CLKA
ENB
4677 drw27
ENA
CLKB
12
tSKEW2
tENS2
tENH
tPAF
tENS2 tENH
tPAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
IDT72V3684L15PF8
Mfr. #:
Manufacturer:
Description:
IC FIFO 32768X36 15NS 128QFP
Lifecycle:
New from this manufacturer.
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