s JEDEC Standard 3.3V Power Supply s The V54C365324V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: and Full Page for Sequential and for Interleave s DQM 0-3 for Byte Masking s Auto & Self Refresh s 2K Refresh ms s Burst Read with Single Write Operation

The 67,108, 864 bits synchronous high data rate DRAM organized x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.

VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC CLK CKE A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS

Row Address Buffer Column Address Counter Latency & Burst Length CLK Programming Register BA0, BA1 Column Address Buffer Row Addresses