Single-Chip ASIC Alternative for Automotive Applications to 54,000 System Gates to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry to 202 User-Programmable I/O Pins

to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Low Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Note: While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial, industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the 40MX and 42MX Family FPGAs datasheet for more details.

Application (Temperature Range) A = Automotive to +125�C) Package Lead Count Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin Quad Flat Pack (1.4 mm) VQ = Very Thin Quad Flat Pack (1.0 mm) Speed Grade (Blank for Standard) Part Number = 3,000 System Gates = 6,000 System Gates = 14,000 System Gates = 24,000 System Gates = 36,000 System Gates = 54,000 System Gates Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available.

Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack

Note: Refer to the 40MX and 42MX Family FPGAs datasheet for details on commercial-, industrial- and military-grade MX offerings.

General Description. 1-1 MX Architectural Overview. 1-1 Other Architectural Features. 1-5 Development Tool Support. 1-11 Related Documents. 1-11 5.0V Operating Conditions. 1-12 Power Dissipation. 1-13 Junction Temperature. 1-15 Package Thermal Characteristics. 1-15 Timing Information. 1-16 Parameter Measurement. 1-19 Sequential Timing Characteristics. 1-20 Decode Module Timing. 1-22 Dual-Port SRAM Timing Waveforms. 1-23 Predictable Performance: Tight Delay Distributions. 1-25 Temperature and Voltage Derating Factors. 1-26 Timing Characteristics. 1-28 Pin Descriptions. 1-45

68-Pin PLCC. 2-1 84-Pin PLCC. 2-3 100-Pin PQFP. 2-5 160-Pin PQFP. 2-8 80-Pin VQFP. 2-11 208-Pin PQFP. 2-13 240-Pin PQFP. 2-17 100-Pin VQFP. 2-20 176-Pin TQFP. 2-23