Single Power Supply Operation � 10% Read/Program/Erase High Performance Read 70/90 ns access time Memory Blocks Architecture - One 16 Kbytes top or bottom Boot Block with software lockout - Two 8 Kbytes Parameter Blocks - One 96 Kbytes Main Block - Three 128 Kbytes Main Blocks Automatic Block Erase and Byte Program - Typical 12 �s/byte programming - Typical 50 ms block or chip erase Hardware Data Protection

Data# Polling and Toggle Bit Features Low Power Consumption - Typical 15 mA active read current - Typical 40 mA program/erase current - Typical 0.1 �A CMOS standby current High Product Endurance - Guarantee 10,000 program/erase cycles - Typical 50,000 program/erase cycles - Minimum 10 years data retention Industrial Standard Pin-out and Packaging - 32-pin Plastic DIP - 32-pin PLCC Manufactured 0.30 �m process

The a 4 Megabit, 5 Volt-only Flash Memory organized as 524,288 bytes of 8 bits each. This device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt VPP power supply for program and erase operation is not required. The device can be programmed in standard EPROM programmers as well. The 4 Megabit memory array is divided into seven blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes, and three 128 Kbytes for BIOS and parameters storage. The seven blocks allow users to flexibly make chip erase or block erase operation. The block erase feature allows a particular block to be erased and reprogrammed without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can be reprogrammed on a byte-by-byte basis. The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pin-out and command set. The program operation Pm29F004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation Pm29F004 is executed by issuing the chip erase or block erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before the erase operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation can be detected by Data# Polling I/O7 or Toggle Bit of I/O6. The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot block is permanently protected from being reprogrammed. The Pm29F004 is manufactured on PMC's advanced 0.30 �m, P-FLASHTM, nonvolatile memory process. The device is packaged a 32-pin DIP and PLCC with access time of 70 and 90 ns.

Temperature Range C = Commercial to +70�C) Package Type = 32-pin Plastic DIP = 32-pin Plastic J-Leaded Chip Carrier (32J) Speed Option Boot Block Location T = Top Boot Block B = Bottom Boot Block PMC Device Number