UPD16772 - 480-OUTPUT TFT-LCD SOURCE DRIVER
UPD16772 Datasheet PDF
Posted Apr 17, 2005 (Stock #: 368604 )
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16772
480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16772 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 26
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0,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input (2.3 to 3.6 V) • 480 outputs • Input of 6 bits (gradation data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC) • Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V • High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Display data inversion function (POL21/22) • Current consumption reduction function (LPC, Bcont) • Logic power supply voltage (VDD1) : 2.3 to 3.6 V • Driver power supply voltage (VDD2) : 8.5 V ± 0.5 V
ORDERING INFORMATION
Part Number Package TCP (TAB package)
µ PD16772N-xxx
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14416EJ1V0DS00 (1st edition) Date Published August 2000 NS CP (K) Printed in Japan
The mark • shows major revised points.
©
1999, 2000
µPD16772
1. BLOCK DIAGRAM
STHR R,/L CLK STB C1 C2 STHL VDD1 VSS1 C79 C80
80-bit bidirectional shift register
D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL21/22
Data register
POL
Latch
VDD2 Level shifter VSS2
V0 - V9
D/A converter
LPC Bcont
Voltage follower output
S1
S2
S3
S480
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1 S2 S479 S480
V0 V4 V5 V9 Multiplexer
5
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