The an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7 the second bit in Q6 the third in Q5 etc The serial input data is also synchronized by an auxiliary flip-flop and brought out on QD Designed primarily for use in the successive approximation technique for analog-to-digital conversion the LS502 can also be used as a serial-to-parallel converter ring counter and as the storage and control element in recursive digital routines

Low power Schottky version of 2502 Storage and control for successive approximation to D conversion Performs serial-to-parallel conversion

Description Serial Data Input Start Input (Active LOW) Clock Pulse Input (Active Rising Edge) Synchronized Serial Data Output Conversion Complete Output (Active LOW) Parallel Register Outputs Complement of Q7 Output

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage 7V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings The ``Recommended Operating Conditions'' table will define the conditions for actual device operation

Symbol VCC VIH VIL IOH IOL TA ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW to CP Hold Time HIGH or LOW to CP Setup Time HIGH or LOW to CP Hold Time HIGH or LOW to CP Pulse Width HIGH or LOW

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min b18 mA VCC e Min IOH e Max VIL e Max VCC Min IOL e Max VIH e Min IOL 4 mA VCC e Min II IIH IIL IOS Input Current Input Voltage Max VCC e Max e 10V VCC e Max 2 7V VCC e Max 0 4V VCC e Max (Note 2) VCC e Max DM54 DM74

Note 1 All typicals are at VCC 25 C Note 2 Note more than one output should be shorted at a time and the duration should not exceed one second

The register stages are composed of transparent RS latches arranged in master slave pairs The master and slave latches are enabled separately by non-overlapping complementary signals w1 and w2 derived internally from the CP input Master latches are enabled when CP is LOW and slave latches are enabled when CP is HIGH Information is transferred from master to slave and thus to the outputs by the LOW-to-HIGH transition of CP Initializing the register requires a LOW signal on S while exercising CP With S and CP LOW all master latches are SET (Q side HIGH) A LOW-to-HIGH CP transition with S remaining LOW then forces the slave latches to the condition wherein Q7 is LOW and all other register outputs including CC are HIGH This condition will prevail as long as S remains LOW regardless of subsequent CP rising edge To start the conversion process S must return to the HIGH state On the next CP rising edge the information stored in the serial data input latch is transferred to QD and Q7 while Q6 is forced to the LOW state On the rising edge of the next seven clocks this LOW signal is shifted downstream one bit at a time while the serial data enters the register position one bit behind this LOW signal as shown in the Truth Table Note that after a serial data bit appears at a particular output that register position undergoes no further changes After the shifted LOW signal reaches CC the register is locked up and no further changes can occur until the register is initialized for the next conversion process

Figure a shows a simplified hook-up D A converter and a comparator arranged to convert an analog input voltage into an 8-bit binary number by the successive approximation technique Figure is an idealized graph showing the various values that the D A converter output voltage can assume in the course of the conversion The vertical axis is calibrated in fractions of the full-scale output capability of the D A converter and the horizontal axis represents the successive states of the Truth Table At time Q7 is LOW and Q6�Q0 are HIGH causing the D A output to be one-half of full scale If the analog input voltage is greater than this voltage the comparator output (hence the D input of the LS502) will be LOW and at times t2 the D A output will rise to three-fourths of full scale because Q7 will remain LOW and contribute 50% while Q6 is forced LOW and contributes another 25% On the other hand if the analog input voltage is less than one-half of full scale the comparator output will be HIGH and Q7 will go HIGH t2 Q6 will still be forced LOW at t2 and the D A output will decrease 25% of full scale Thus with each successive clock the D A output will change by smaller increments When the conversion is completed at t9 the binary number represented by the register outputs will be the numerator of the fraction n 256 representing the analog input voltage as a fraction of the full scale output D A converter