Common features: � Low input and output leakage 1�A (max.) � CMOS power levels � True TTL input and output compatibility � VOH = 3.3V (typ.) � VOL = 0.3V (typ.) � Meets or exceeds JEDEC standard 18 specifications � Product available in Radiation Tolerant and Radiation Enhanced versions � Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) � Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages Features for B, C and D speed grades � High drive outputs (-15mA IOH, 48mA IOL) � Power off disable outputs permit "live insertion"

The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) � ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high IOL/IOH. The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.

Description The D flip-flop data inputs. When the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-toHIGH transition. The register 3-state outputs. Clock Enable. When the clock enable is LOW, data on the D I input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Y I outputs are in the highimpedance state. When the OE input is LOW, the TRUE register data is present at the YI outputs.

Symbol Rating Commercial (2) VTERM Terminal Voltage to +7.0 with Respect to GND VTERM(3) Terminal Voltage �0.5 to with Respect to VCC +0.5 GND TA Operating to +70 Temperature TBIAS Temperature to +125 Under Bias TSTG Storage to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current to +120 Military to +7.0 Unit V

Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit pF 12

2567 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.