32 Megabit x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features

AMD-supplied software manages data programming and erasing, enabling EEPROM emulation Eases sector erase limitations

Data can be continuously read from one bank while executing erase/program functions in other bank Zero latency between read and write operations

Read may occur in any of the three banks not being written or erased. Four banks may be grouped by customer to achieve desired bank divisions.

Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. Customer lockable: Sector is one-time programmable. Once locked, data cannot be changed

Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status Acceleration (ACC) function accelerates program timing

Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero

Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector Temporary Sector Unprotect allows changing data in protected sectors in-system

I Top or bottom boot block I Manufactured 0.17 �m process technology I Compatible with JEDEC standards

CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: to 3.3 volt Byte data control: LB#s (DQ7�DQ0), UB#s (DQ15�DQ8)

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

The Am29DL320G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data app � DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The devices are available with access times of 70 and 85 ns. The device is offered a 73-ball FBGA package. Standard control pins-- chip enable (CE#f), write enable (WE#), and output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. some previous AMD 32 Mbit Am29DL32x devices had a larger SecSi Sector. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), or both. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory devi vi e. user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses he F lash memo b y callin g one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device allows a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL320G can be organized as either a top or bottom boot sector configuration. Bank 1 Bank 2 Bank 3 Bank 4 Megabits 4 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Eight 64 Kbyte/32 Kword

The SecSi TM (Secured Silicon) Sector an 256 byte extra sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set 1 if the part is factory locked , and set 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Note that

Product Selector Guide. 5 MCP Block Diagram. 5 Flash Memory Block Diagram. 6 Connection Diagram. 7 Special Handling Instructions for FBGA Package.................... 7 Pin Description. 8 Logic Symbol. 8 Ordering Information. 9 Device Bus Operations. 10

Table 1. Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC..................................................... 11 Table 2. Device Bus Operations--Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS......................................................12 Table 3. Device Bus Operations--Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIOs = VCC.....................................................13 Table 4. Device Bus Operations--Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS..................................................................14

Reset Command..................................................................... 28 Autoselect Command Sequence............................................ 28 Enter SecSi Sector/Exit SecSi Sector Command Sequence.. 29 Byte/Word Program Command Sequence............................. 29 Unlock Bypass Command Sequence.................................. 29

Chip Erase Command Sequence........................................... 30 Sector Erase Command Sequence........................................ 30 Erase Suspend/Erase Resume Commands........................... 31

Figure 4. Erase Operation.............................................................. 31 Table 15. Command Definitions (Flash Word Mode)...................... 32 Table 16. Command Definitions (Flash Byte Mode)....................... 33

Word/Byte Configuration........................................................ 15 Requirements for Reading Array Data................................... 15 Writing Commands/Command Sequences............................ 15 Accelerated Program Operation.......................................... 15 Autoselect Functions........................................................... 15 Simultaneous Read/Write Operations with Zero Latency....... 15 Standby Mode........................................................................ 16 Automatic Sleep Mode........................................................... 16 RESET#: Hardware Reset Pin............................................... 16 Output Disable Mode.............................................................. 16

Table 5. Device Bank Division........................................................16 Table 6. Top Boot Sector Addresses.............................................17 Top Boot SecSi Sector Addresses............................................. 18 Table 8. Bottom Boot Sector Addresses.........................................19 Bottom Boot SecSi Sector Addresses........................................ 20

DQ2: Toggle Bit II................................................................... 36 Reading Toggle Bits 36 DQ5: Exceeded Timing Limits................................................ 36 DQ3: Sector Erase Timer....................................................... 36

Absolute Maximum Ratings. 38 Operating Ranges. 38 Industrial (I) Devices............................................................ 38 VCCf/VCC s Supply Voltage................................................... 38 DC Characteristics. 39 CMOS Compatible.................................................................. 39 SRAM DC and Operating Characteristics. 40 Zero-Power Flash................................................................. 41

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)........................................................................................ 41 Figure 10. Typical ICC1 vs. Frequency............................................ 41

Autoselect Mode..................................................................... 21 Sector/Sector Block Protection and Unprotection.................. 21

Figure 11. Test Setup.................................................................... 42 Table 18. Test Specifications......................................................... 42

Write Protect (WP#)................................................................ 21 Temporary Sector/Sector Block Unprotect............................. 22

Figure 1. Temporary Sector Unprotect Operation........................... 22 Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms.............................................................................................. 23

SecSi (Secured Silicon) Sector Flash Memory Region.......... 24 Factory Locked: SecSi Sector Programmed and Protected At the Factory.......................................................................... 24 Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory........................................................... 24 Hardware Data Protection...................................................... 24 Low VCC Write Inhibit........................................................... 24 Write Pulse "Glitch" Protection............................................ 24 Logical Inhibit...................................................................... 24 Power-Up Write Inhibit......................................................... 25 Common Flash Memory Interface (CFI). 25

Table 11. CFI Query Identification String........................................ 25 System Interface String................................................................... 26 Table 13. Device Geometry Definition............................................ 26 Table 14. Primary Vendor-Specific Extended Query...................... 27

Figure 16. CIOf Timings for Read Operations................................ 46 Figure 17. CIOf Timings for Write Operations................................ 46

Figure 18. Program Operation Timings.......................................... Figure 19. Accelerated Program Timing Diagram.......................... Figure 20. Chip/Sector Erase Operation Timings.......................... Figure 21. Back-to-back Read/Write Cycle Timings...................... Figure 22. Data# Polling Timings (During Embedded Algorithms). Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... Figure 24. DQ2 vs. DQ6.................................................................