The is 64M words � 64 bits, 2 ranks DDR2 SDRAM unbuffered module, mounting 16 pieces of 512M bits DDR2 SDRAM sealed in FBGA (�BGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4 bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (�BGA) on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.

240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm 1.8V power supply Data rate: 533Mbps/400Mbps (max.) 1.8V (SSTL_18 compatible) I/O Double-data-rate architecture: two data transfers per clock cycle Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver DQS is edge aligned with data for READs: centeraligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS Four internal banks for concurrent operation (Component) Data mask (DM) for write data Burst lengths: 4, 8 /CAS Latency (CL): 4, 5 Auto precharge operation for each burst access Auto refresh and self refresh modes 7.8�s average periodic refresh interval Posted CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality /DQS can be disabled for single-ended Data Strobe operation.

Document No. E0365E10 (Ver. 1.0) Date Published March 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003

Part number EBE11UD8ABFA-4A EBE11UD8ABFA-4C Data rate Mbps (max.) 533 400 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-400 (4-4-4) Package 240-pin DIMM Contact pad Gold Mounted devices EDE5108ABSE

Pin No. Pin name DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26 DQ27 VSS NC VSS NC VSS NC VSS VDDQ CKE0 VDD NC VDDQ A11 A7 VDD A5 Pin No. Pin name DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. Pin name DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS NC VSS NC VSS NC VSS VDDQ CKE1 VDD NC VDDQ A12 A9 VDD A8 A6 Pin No. Pin name VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 /CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1