EBE51UD8AGFA

DATA SHEET www.DataSheet4U.com 512MB Unbuffered DDR2 SDRAM DIMM EBE51UD8AGFA (64M words × 64 bits, 1 Rank) Description The EBE51UD8AGFA is 64M words × 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the

More View

/CK. This highspeed data transfer is realized by the 4 bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features • 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 667Mbps/533Mbps/400Mbps (max.) • SSTL_18 compatible I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation (components) • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • Average refresh period  7.8µs at 0°C ≤ TC ≤ +85°C  3.9µs at +85°C < TC ≤ +95°C • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation Document No. E0781E20 (Ver. 2.0) Date Published October 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005 EBE51UD8AGFA Ordering Information Part number EBE51UD8AGFA-6E-E EBE51UD8AGFA-5C-E EBE51UD8AGFA-4A-E Data rate Mbps (max.) 667 533 400 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) 240-pin DIMM (lead-free) Gold Package Contact pad www.DataSheet4U.com Mounted devices EDE5108AGSE-6E-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E EDE5108AGSE-4A-E Pin Configurations Front side 1 pin 64 pin 65 pin 120 pin 121 pin Back s