High-performance, cost-effective, low-power 0.35 �m CMOS technology 0.3 �m CMOS technology (OR2TxxA), and 0.25 �m CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis) Four 16-bit look-up tables and four latches/flip-flops per PFU, nibble-oriented for implementing 8-, 16-, and/or 32-bit (or wider) bus structures Eight 3-state buffers per PFU for on-chip bus structures Fast, on-chip user SRAM has features to simplify RAM design and increase RAM speed: Asynchronous single port: 64 bits/PFU Synchronous single port: 64 bits/PFU Synchronous dual port: 32 bits/PFU Improved ability to combine PFUs to create larger RAM structures using write-port enable and 3-state buffers Fast, dense multipliers can be created with the multiplier mode x 1 multiplier/PFU): x 8 multiplier requires only 16 PFUs 30% increase in speed Flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable Enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation

Innovative, abundant, and hierarchical nibbleoriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance Upward bit stream compatible with the ORCA ATT2Cxx/ ATT2Txx series of devices Pinout-compatible with new ORCA Series 3 FPGAs TTL or CMOS input levels programmable per pin for the (5 V) devices Individually programmable drive capability: sink/6 mA source sink/3 mA source Built-in boundary scan (IEEE *1149.1 JTAG) and 3-state all I/O pins, (TS_ALL) testability functions Multiple configuration options, including simple, low pincount serial ROMs, and peripheral or JTAG modes for insystem programming (ISP) Full PCI bus compliance for all devices Supported by industry-standard CAE tools for design entry, synthesis, and simulation with ORCA Foundry Development System support (for back-end implementation) New, added features (OR2TxxB) have: More I/O per package than the OR2TxxA family No dedicated 5 V supply (VDD5) Faster configuration speed (40 MHz) Pin selectable I/O clamping diodes provide or 3.3V PCI compliance and 5V tolerance Full PCI bus compliance in both 5V and 3.3V PCI systems

* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The second number assumes of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing x 4 RAM (or 256 gates) per PFU.

Features...................................................................... 1 Description................................................................... 3 ORCA Foundry Development System Overview......... 5 Architecture................................................................. 5 Programmable Logic Cells.......................................... 5 Programmable Function Unit................................... 5 Look-Up Table Operating Modes............................ 7 Latches/Flip-Flops................................................. 15 PLC Routing Resources........................................ 17 PLC Architectural Description................................ 22 Programmable Input/Output Cells............................. 25 Inputs..................................................................... 25 Outputs.................................................................. 5 V Tolerant I/O (OR2TxxB).................................. 27 PCI Compliant I/O.................................................. 27 PIC Routing Resources......................................... 28 PIC Architectural Description................................. 29 PLC-PIC Routing Resources................................. 30 Interquad Routing...................................................... 32 Subquad Routing (OR2C40A/OR2T40A Only)...... 34 PIC Interquad (MID) Routing................................. 36 Programmable Corner Cells...................................... 37 Programmable Routing.......................................... 37 Special-Purpose Functions.................................... 37 Clock Distribution Network........................................ 37 Primary Clock........................................................ 37 Secondary Clock................................................... 38 Selecting Clock Input Pins..................................... 39 FPGA States of Operation......................................... 40 Initialization............................................................ 40 Configuration......................................................... 41 Start-Up................................................................. 42 Reconfiguration..................................................... 42 Partial Reconfiguration.......................................... 43 Other Configuration Options.................................. 43 Configuration Data Format........................................ 43 Using ORCA Foundry to Generate Configuration RAM Data..................................... 44 Configuration Data Frame..................................... 44 Bit Stream Error Checking......................................... 47 FPGA Configuration Modes....................................... 47 Master Parallel Mode............................................. 47 Master Serial Mode............................................... 48 Asynchronous Peripheral Mode............................ 49 Synchronous Peripheral Mode.............................. 49 Slave Serial Mode................................................. 50 Slave Parallel Mode............................................... 50 Daisy Chain........................................................... 51 Special Function Blocks............................................ 52 Single Function Blocks.......................................... 52 Boundary Scan...................................................... 54 2

Boundary-Scan Instructions...................................55 ORCA Boundary-Scan Circuitry............................56 ORCA Timing Characteristics....................................60 Estimating Power OR2TxxA...............................................................63 OR2T15B and OR2T40B.......................................65 Pin Information..........................................................66 Pin Descriptions.....................................................66 Package Compatibility...........................................68 Compatibility with Series 3 FPGAs........................70 Package Thermal QJC......................................................................126 QJB......................................................................126 Package Coplanarity...............................................127 Package Parasitics..................................................127 Absolute Maximum Ratings.....................................129 Recommended Operating Conditions......................129 Electrical Characteristics.........................................130 Timing Characteristics.............................................132 Series 2................................................................160 Measurement Conditions.........................................169 Output Buffer OR2TxxA.............................................................171 OR2TxxB.............................................................172 Package Outline Drawings......................................173 Terms and 432-Pin EBGA.....................................................186 Ordering Information................................................187 Index........................................................................189

mable input/output cells (PICs). An array of PLCs is surrounded by PICs as shown in Figure 1. Each PLC contains a programmable function unit (PFU). The PLCs and PICs also contain routing resources and configuration RAM. All logic is done in the PFU. Each PFU contains four 16-bit look-up tables (LUTs) and four latches/flip-flops (FFs). The PLC architecture provides a balanced mix of logic and routing that allows a higher utilized gate/PFU than alternative architectures. The routing resources carry logic signals between PFUs and I/O pads. The routing in the PLC is symmetrical about the horizontal and vertical axes. This improves routability by allowing a bus of signals to be routed into the PLC from any direction. Some examples of the resources required and the performance that can be achieved using these devices are represented in Table 2.

The ORCA Series 2 series of SRAM-based FPGAs are an enhanced version of the ATT2C/2T architecture. The latest ORCA series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of PLCs and routing resources. The Series 2 devices can be used as drop-in replacements for the ATT2Cxx/ATT2Txx series, respectively, and they are also bit stream compatible with each other. The usable gate counts associated with each series are provided in Table 1. Both series are offered in a variety of packages, speed grades, and temperature ranges. The ORCA series FPGA consists of two basic elements: programmable logic cells (PLCs) and programTable 2. ORCA Series 2 System Performance Function 16-bit loadable up/down counter 16-bit accumulator x 8 parallel multiplier: Multiplier mode, unpipelined1 ROM mode, unpipelined2 Multiplier mode, x 16 RAM: Single port (read and write/ cycle)4 Single port5 Dual port6 36-bit parity check (internal) 32-bit address decode (internal)

Implemented using x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. Implemented using two x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. Implemented using x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output of 44 PFUs contain only pipelining registers). Implemented using x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address multiplexer. Implemented using x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address multiplexer. Implemented using x 2 synchronous dual-port RAM mode. OR2TxxB available only in -7 and -8 speeds only. Speed grades -5, -6, and -7 are for OR2TxxA devices only.