The Samsung a 8M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM378S823CT consists of nine CMOS x 8 bit Synchronous DRAMs in TSOP-II 400mil packages, two 20 bits Drive ICs for input control signal and one PLL in 24-pin TSOP package mounted a 200-pin glass-epoxy substrate. Two 0.1uF decopling capacitors are mounted on the printed circuit board for each SDRAM. The is a Dual In-line Memory Module and is intended for mounting into 200-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Burst Mode Operation Auto & Self Refresh Capability (4096 cycles / 64ms) LVTTL compatible inputs and outputs Single � 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length Full page) Data Scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock PCB : Height(1,250mil), double sided component

Pin Front VDD NC *IN *OUT NC VSS DQ67 DQ66 VDDQ DQ65 DQ64 VSS DQ61 DQ60 VDDQ NC VSS NC Pin Front VDDQ DQ51 DQ50 VSS DQ49 DQ48 VDDQ DQ43 DQ42 VSS DQ41 DQ40 VDDQ A4 A5 VSS A8 A9 VDD NC CKE0 VSS CAS NC VDD Pin Front Pin Front DQ16 VSS NC VDDQ DQ15 DQ14 VSS DQ13 DQ12 VDDQ DQ7 DQ6 VSS DQ5 DQ4 VDDQ NC SCL NC VSS Pin Back NC VSS REGE RFU DQ71 DQ70 VSS DQ69 DQ68 VDDQ NC VSS DQ59 DQ58 VSS DQ57 DQ56 VDDQ DQ55 DQ54 VSS Pin Back Pin Back Pin Back VDD(Q) NC VSS NC VDDQ DQ11 DQ10 VSS DQ9 DQ8 VDDQ DQ3 DQ2 VSS DQ1 DQ0 SDA SA1 SA2 VDD NC 51 VSS 76 52 RAS 77 53 VSS 80 56 VDD 83 59 VSS 86 62 VDDQ 89 65 VSS 92 68 VDDQ 95 71 VSS 98 74 VDDQ 176 152 VDD NC 128 VDDQ 130 DQ46 VSS 156 131 VSS 133 DQ44 VDD 159 134 VDDQ 136 DQ38 VSS 162 137 VSS 139 DQ36 VDDQ 189 140 VDD A7 167 VSS 168 143 VSS 145 NC VDDQ 195 146 VDD 172 147 DQM WE 173 VSS 198 VSS NC 200

Note :1. ; These pins are not used in this synchronous DRAM module. Here these pins are equal to No Connection. 2. In LVTTL interface, VDDQ=VDD and VSSQ=VSS

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin Name CKE0 CS0 RAS CAS WE DQM REGE *IN, *OUT ~ SA2 **SDA **SCL VDD VDDQ Vss RFU NC Function Address Input (multiplexed) SDRAM Bank Select Data Inputs / Outputs Clock Input Clock Enable Input Chip Select Input Row Address Storbe Colume Address Strobe Write Enable DQ Mask Enable Buffer Enable Unbuffered Physical Detect Input/Output (separate) Address input for EEPROM Serial Data I/O for PD Clock Input for PD Power Supply Power supply for Data Input/Output Ground Reserved Future Use No Connection CLK CS Clock input

Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down standby. Row & column address are multiplexed on the same pins. Row address:RA0~RA11, Column address:CA0~CA8

Selects bank to be activated during row address latch BA0,BA1 time and selects bank for read/wirte during column address latch time. RAS CAS WE DQM DQ Latches row address on the positive edge of the CLK with RAS low. Enables row access & precharge. Latches column address on the positive edge of the CLK with RAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS ,WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data intput when DQM active Data inputs/outputs are multiplexed on the same pins. The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VCC through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode.

* These pins are not used in this module. These pins should NC in the system which does not support SPD.