• User selectable HSTL/LVTTL Input and/or Output
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Output voltage
• 3.3V Input tolerant
• Program programmable flags by either serial or parallel means
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 240-pin PBGA package
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• Industrial temperature range (–40C to +85C) is available

to 225 MHz Operation of Clocks User selectable HSTL/LVTTL Input and/or Output Read Enable & Read Clock Echo outputs aid high speed operation User selectable Asynchronous read and/or write port timing 2.5V LVTTL 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage 3.3V Input tolerant Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for Almost-

Separate SCLK input for Serial programming of flag offsets User selectable input and output port bus-sizing

to x9 out to x18 out to x9 out to x18 out Big-Endian/Little-Endian user selectable byte representation Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function Available x 19mm) PlasticBall Grid Array (PBGA) Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology

Industrial temperature range +85�C) is available Green parts are available, see ordering information For IDT72T1845/55/65/75/85/95 functional replacement device use

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only PBGA: 1mm pitch, 13mm BB144 (Order code: BB) TOP VIEW