Low power 90 mA max. commercial (10 ns) 130 mA max. commercial (5 ns) CMOS Flash EPROM technology for electrical erasability and reprogrammability Variable product terms 2 x(8 through 16) product terms User-programmable macrocell Output polarity control Individually selectable for registered or combinatorial operation to 22 input terms and 10 outputs DIP, LCC, and PLCC available 5 ns commercial version 4 ns tCO 5 ns tPD 181-MHz state machine 10 ns military and industrial versions 7 ns tCO 10 ns tPD 110-MHz state machine 15-ns commercial, industrial, and military versions 25-ns commercial, industrial, and military versions High reliability Proven Flash EPROM technology 100% programming and functional testing

The Cypress is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell.

The PALCE22V10 is executed 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides to 22 inputs and 10 outputs. The PALCE22V10 can be electrically erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as "registered" or "combinatorial." Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through "array" configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALCE22V10 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing to 16 product terms per output. By providing this variable structure, the PALCE 22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the to 800-gate-array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, func-

tions requiring to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability.

Registered/Combinatorial C1 C0 Configuration Registered/Active LOW Registered/Active HIGH Combinatorial/Active LOW Combinatorial/Active HIGH

(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature................................. to +150�C Ambient Temperature with Power Applied............................................. to +125�C Supply Voltage to Ground Potential (Pin 24 to Pin +7.0V DC Voltage Applied to Outputs in High Z State............................................... +7.0V DC Input Voltage............................................ to +7.0V Output Current into Outputs (LOW).............................16 mA

DC Programming Voltage............................................. 12.5V Latch-Up Current..................................................... >200 mA Static Discharge Voltage (per MIL-STD-883, Method 3015)............................. >2001V