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A54SX16A-FCQ208 Datasheet(PDF) 60 Page - Actel Corporation |
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A54SX16A-FCQ208 Datasheet(HTML) 60 Page - Actel Corporation |
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60 / 108 page  SX-A Family FPGAs 2- 40 v5.3 Table 2-33 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C) Parameter Description –3 Speed1 –2 Speed –1 Speed Std. Speed –F Speed Units Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 3.3 V PCI Output Module Timing2 tDLH Data-to-Pad Low to High 1.9 2.2 2.4 2.9 4.0 ns tDHL Data-to-Pad High to Low 2.0 2.3 2.6 3.1 4.3 ns tENZL Enable-to-Pad, Z to L 1.4 1.7 1.9 2.2 3.1 ns tENZH Enable-to-Pad, Z to H 1.9 2.2 2.4 2.9 4.0 ns tENLZ Enable-to-Pad, L to Z 2.5 2.8 3.2 3.8 5.3 ns tENHZ Enable-to-Pad, H to Z 2.0 2.3 2.6 3.1 4.3 ns dTLH 3 Delta Low to High 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL 3 Delta High to Low 0.015 0.015 0.015 0.015 0.025 ns/pF 3.3 V LVTTL Output Module Timing4 tDLH Data-to-Pad Low to High 2.6 3.0 3.4 4.0 5.6 ns tDHL Data-to-Pad High to Low 2.6 3.0 3.3 3.9 5.5 ns tDHLS Data-to-Pad High to Low—low slew 9.0 10.4 11.8 13.8 19.3 ns tENZL Enable-to-Pad, Z to L 2.2 2.6 2.9 3.4 4.8 ns tENZLS Enable-to-Pad, Z to L—low slew 15.8 18.9 21.3 25.4 34.9 ns tENZH Enable-to-Pad, Z to H 2.6 3.0 3.4 4.0 5.6 ns tENLZ Enable-to-Pad, L to Z 2.9 3.3 3.7 4.4 6.2 ns tENHZ Enable-to-Pad, H to Z 2.6 3.0 3.3 3.9 5.5 ns dTLH 3 Delta Low to High 0.025 0.03 0.03 0.04 0.045 ns/pF dTHL 3 Delta High to Low 0.015 0.015 0.015 0.015 0.025 ns/pF dTHLS 3 Delta High to Low—low slew 0.053 0.053 0.067 0.073 0.107 ns/pF Notes: 1. All –3 speed grades have been discontinued. 2. Delays based on 10 pF loading and 25 Ω resistance. 3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation: Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]) where Cload is the load capacitance driven by the I/O in pF dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF. 4. Delays based on 35 pF loading. |
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