8-bit Nonvolatile Latch Logic state is preserved in the absence of power Over 10 Billion (1010 ) nonvolatile state changes Advanced high-reliability ferroelectric process Operates like conventional CMOS logic Transparent (573) or D-Flip-flop (574) operation FM573 transparent for C high, latched for C low FM574 data is clocked on the rising edge 33/80 ns data propagation delay 30 MHz/12 MHz Maximum frequency (5V/3V) Automatic Nonvolatile Operation Latched state is stored automatically State is automatically restored on power-up Power supply monitor prevents low-VDD writes Low Power Operation Supply voltage 125 �A standby current Industry Standard Configuration Industrial temperature C 20-pin SOP or DIP

The FM573 and FM574 are innovative circuits that store inputs like conventional logic families, and then retain the stored state in the absence of power. These products solve three basic problems in an elegant fashion. First, they provide continuous access to nonvolatile system settings without performing a memory read operation or using dedicated processor I/O pins. Second, they allow the storage of signals or data that may change frequently and possibly without notice. Third, they allow the nonvolatile storage of a few bits of data or system settings without the system overhead and extra pins of a serial memory. The is a transparent latch. The inputs are passed to the outputs when the clock is high; the state is latched when the clock goes low. The is a Dtype register. Inputs are stored and passed to the outputs on the rising edge of the clock. The nonvolatile latch is a unique product that serves a variety of applications. A few ideas as follows: � Controls relays and valves with automatic setting on power-up without processor intervention. � Interface to soft/momentary front-panel switches and indicator lamps. Capture switch settings and light LED's without processor intervention. � Replaces jumpers & control signal routing � Initialize state of I/O card signals. � Save system errors or status codes when power fails with a fast, no overhead write and automatic restore on power up. � Eliminate the overhead of serial memory for systems needing only a few bits of data. The FM573 and FM574 are provided a 20-pin DIP or SOP. They are rated from to +85C.

This data sheet contains specifications for a product under development. Characterization is not complete; specifications may change without notice.

FM574-P FM574-S Transparent latch, 20-pin plastic DIP Transparent latch, 20-pin SOP Register, 20-pin plastic DIP Register, 20-pin SOP

Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, (719) 481-7000, Fax (719) 481-7058

Pin Description Pin Name /OE D0-D7 Q0-Q7 VSS VDD Pin Number I/O Pin Description Output enable. When low, the outputs are driven. When high, the outputs are tri-stated. Controls the latching of data according to the truth tables below. Data in. Data out. Ground Supply Voltage

FM573 Table /OE X Dn Internal Qn Dn Output Qn Hi-Z Qn Dn Hi-Z Description Tri-state outputs Outputs enabled, hold state Transparent Load data, outputs tri-state

FM574 Table /OE X Dn Internal Qn Dn Output Qn Hi-Z Qn Dn Hi-Z Description Tri-state outputs Outputs enabled, hold state Load data, outputs enabled Load data, outputs tri-state

FM573/574 This power up sequence occurs as follows. On detection of a power-up, the internal nonvolatile latch is read. This value is then placed on an internal version of the Dn input. A single internal clock is generated to cause the user latch to accept the restored data. After this process is comp lete, the latch provides normal user-controlled operation. Users should not attempt to latch externally supplied data prior to tPUH after VDD reaches VMIN. The following diagram illustrates the power-up and down sequences. Figure 2. Power Cycle Flow Chart

Nonvolatile logic is a revolutionary product family that simplifies the design of system control functions. The is a transparent octal latch; the is an octal D-type register. These products are unique because the stored values also are retained in the absence of power. They are pin and functionally compatible with their industry standard CMOS equivalents. Any change in the latched state automatically is written into a nonvolatile ferroelectric latch. This function is possible due to the fast write time and extremely high write endurance of the underlying ferroelectric memory technology. A new state becomes nonvolatile no more than ns (VDD=5V) after the write begins. Users interface to a conventional latch rather than directly to the nonvolatile latch. Equivalent ferroelectric nonvolatile latches shadow the user's latches. They offer a very high but not unlimited number of write-cycles. Therefore, the internal state machine writes to the nonvolatile latch only if the latched state has changed in order to minimize the actual number of nonvolatile write-cycles. This determination is made independently for each bit. Due to the short write-time and realistic power slew rates, it is virtually impossible for the system to lose power before the nonvolatile state is acquired. Power Down Sequence An internal power monitor blocks updates to the nonvolatile latch when VDD is below V MIN (internal voltage reference). The power supply monitor also blocks write access to the user latch when VDD is below V MIN. To guarantee a proper nonvolatile write of the last value, state changes should cease tPDS before VDD reaches VMIN. The VMIN threshold is low enough that no special action may be needed in systems with slow slew rates. For fast power supply slew-rates or for systems that run down to relatively low supply voltages, the user should employ some form of low-VDD reset that trips above VMIN. Power Up The VMIN threshold is a critical parameter for several aspects of product operations. On power-up, the FM573/574 automatically restores the Qn outputs (and internal latches) to the previously stored state. This process begins as VDD rises to V MIN and is completed tRES afterward. Thus for all practical purposes, the nonvolatile values have been restored as soon as the system logic is functional on powerup. After the restore process, the latch is indistinguishable from its last state prior to power down and operates normally.