This specification contains information about the Samsung Electronics Company OneNAND, Flash memory product family. Section 1.0 includes a general overview, revision history, and product ordering information. Section 2.0 describes the OneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the OneNAND. Package dimensions are found in Section 8.0

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. OneNAND�, is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their rightful owners. Copyright 2005, Samsung Electronics Company, Ltd

0.0 0.1 Initial issue. 1. Corrected Errata 2. Revised cache read flow chart 3. Revised standby current 4. Revised spare area description 5. Added CE don't care state for Asynch Write, Load, Program, and Block Erase timing diagram 1. Added Copy Back Operation with Random Data Input 2. Changed tBA from 11.5ns 3. Pended Active Erase Current

1. Corrected the errata Jan. 2005 2. Revised typical value of ISB from 10uA 3. Revised maximum value of ISB from 50uA 4. Revised maximum value of tCE, tAA and tACC from 76ns 5. Revised Vcc-IO description 6. Revised Spare Area description 7. Added extra information on Controller Status Register 8. Added commands related to Interrupt Status Register bits 9. Revised Write Protection Status on Chapter 3.4.3 10. Revised Copy-Back Program Operation description 11. Added extra information on Multi-Block Erase Operation 12. Disabled FBA restriction in OTP operation 13. Revised Cache Read Flow Chart 14. Revised Reset Parameter descriptions 15. Added RDY information on Warm Reset Timing diagram 16. Added information on Data Protection Timing During Power Down 17. Revised Interrupt pin rise and falling slope graph 18. Added restriction on address register setting on Dual Operations 19. Added restriction on address register setting on Cache Read Operation 1. Corrected the errata 2. Updated DC parameters to RMS values 3. Added Speed Information on Product Number 4. Revised tOEZ description 5. Revised OTP register setting restriction 6. Added Boot Sequence Infrormation on Technical Notes 7. Added Cint Information Feb. 25, 2005