e and SYMBOL PARAMETER MAX. UNIT
in level power
astic surlace VD5 Continuous drain ce voltage 50 V
nded as a lD Continuous drain nt 26 A
on for PD Total power diss 75 W
and other T Continuous junc mperature 150 'C
HDSION, Drainrsource one esistance 60 mg
Ii5L Input supply curr V‘S : 5 V 650 pA
r driving
.
.
.
.
- ower DMOS output
‘ @ DRAIN
- tate resistance
- protection against
perature
- protection against V
uit load MP
- overload protection if-
"put ‘ ‘ INPUT K—l POWER
- compatible Input level MOSFET
- r power MOSFET @ fl ,7
ly of overload i
n circuits LO
om input
- perating input current PR0 J E
irect drive by
ntroller ‘
- ection on input pin
- age clamping for turn
uctive loads @ SOURCE
Fig.1. PFET.
PIN DESC TION D
1 input ‘ T , \
2 drain ‘
3 source \
0
mb drain 7 , L
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
DESCRIPTION QUICK REFERENCE DATA
Monolithic temperature and SYMBOL PARAMETER MAX. UNIT
overload protected logic level power
MOSFET in a 3 pin plastic surface VDS Continuous drain source voltage 50 V
mount envelope, intended as a IDContinuous drain current 26 A
general purpose switch for PDTotal power dissipation 75 W
automotive systems and other TjContinuous junction temperature 150 ˚C
applications. RDS(ON) Drain-source on-state resistance 60 mΩ
APPLICATIONS IISL Input supply current VIS = 5 V 650 µA
General controller for driving
lamps
motors
solenoids
heaters
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Lower operating input current
permits direct drive by
micro-controller
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
Fig.1. Elements of the TOPFET.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 drain
3 source
mb drain
POWER
MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
RIG
13
mb
2
P
D
S
I
TOPFET
June 1996 1 Rev 1.000
SYMBOL PA C
VD5 Continuous d voltage‘ , , 50 V
V‘S Continuous in , 0 6 V
|D Continuous d Tmhs25 'C; v = 5 , 26 A
|D Continuous d Tmhs100 'C; : V , 16 A
law Repetitive pe drain current Tm S 25 ‘C; V : 5 V , 100 A
PD Totai power d Tm S 25 ‘C , 75 W
Tslg Storage temp , 755 150 'C
T‘ Continuous ju perature2 normal opera n , 150 'C
Tsum Lead tempera during soider , 250 'C
SYMBOL P C
viSP P to
Ove
vwm Pm age vis
Short
VDDW) Prote v‘S : 5 , 20 V
voitag
PDSM Instan ion Tm _ , 1.3 kW
SYMBOL P C
|DRUM Repetit nt v‘S : 0 , 26 A
EDSM Nonrre Tm S 2 , , 625 mJ
VDD S 2 load
EDRM Repetit Tm S 9 , 40 mJ
vDD : 2
SYM L P C
VC Ele Hu
voi
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Continuous drain source voltage1 - - 50 V
VIS Continuous input voltage - 0 6 V
IDContinuous drain current Tmb ≤ 25 ˚C; VIS = 5 V - 26 A
IDContinuous drain current Tmb ≤ 100 ˚C; VIS = 5 V - 16 A
IDRM Repetitive peak on-state drain current Tmb ≤ 25 ˚C; VIS = 5 V - 100 A
PDTotal power dissipation Tmb ≤ 25 ˚C - 75 W
Tstg Storage temperature - -55 150 ˚C
TjContinuous junction temperature2 normal operation - 150 ˚C
Tsold Lead temperature during soldering - 250 ˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VISP Protection supply voltage3 for valid protection 4 - V
Over temperature protection
VDDP(T) Protected drain source supply voltage VIS = 5 V - 50 V
Short circuit load protection4
VDDP(P) Protected drain source supply VIS = 5 V - 20 V
voltage5
PDSM Instantaneous overload dissipation Tmb = 25 ˚C - 1.3 kW
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
IDROM Repetitive peak clamping current VIS = 0 V - 26 A
EDSM Non-repetitive clamping energy Tmb ≤ 25 ˚C; IDM = 26 A; - 625 mJ
VDD ≤ 20 V; inductive load
EDRM Repetitive clamping energy Tmb ≤ 95 ˚C; IDM = 8 A; - 40 mJ
VDD ≤ 20 V; f = 250 Hz
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCElectrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional.
4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDDP(P) maximum.
June 1996 2 Rev 1.000
SYMBOL P C M T M X U T
Therm
Rm,”b Junctio e , , 1.3 1.67 K/W
Rm,a Junctio minimu , 50 K/W
(see fig
SYMBOL P C M T P. MAX. U T
VLCLWSS Drainrsourc ng voltage V;S : 0 V; ID 50 V
V;CUDSS Drainrsourc ng voltage V;S : 0 V; ID 300 us; , 70 V
B < 0.01="" |dss="" zero="" input="" v="" rain="" current="" ,="" 0.5="" 10="" ua="" |dss="" zero="" input="" v="" rain="" current="" ,="" 1="" 20="" ua="" |dss="" zero="" input="" v="" rain="" current="" :="" 125="" 'c="" ,="" 10="" 100="" 0a="" rdsqn,="" drainrsourc="" te="" v;s="" :="" 5="" v;="" id="" 300="" us;="" ,="" 45="" 60="" m9="" resistance‘="" 6="" s="" 0.01="" symbol="" p="" c="" m="" t="" m="" u="" t="" short="" ction2="" tm="" :="" 2="" 10="" mg="" eden)="" overlo="" y="" vdd="" :="" ,="" 0.4="" j="" m="" respo="" vdd="" :="" ,="" 0.8="" ms="" imo)="" drain="" (2="" vw="" :="" ,="" 45="" a="" imo)="" peak="" d="" v;s="" _="" 5="" .="" 105="" a="" 0v="" n="" tum)="" th="" ure="" v;s="" 1="" 0="" sym="" l="" p="" c="" m="" .="" t="" p.="" m="" u="" t="" 91.="" f0="" v95="" ;="" 10="" 16="">Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
Rth j-mb Junction to mounting base - - 1.3 1.67 K/W
Rth j-a Junction to ambient minimum footprint FR4 PCB - 50 - K/W
(see fig. 23)
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA 50 - - V
V(CL)DSS Drain-source clamping voltage VIS = 0 V; IDM = 2 A; tp ≤ 300 µs; - - 70 V
δ ≤ 0.01
IDSS Zero input voltage drain current VDS = 12 V; VIS = 0 V - 0.5 10 µA
IDSS Zero input voltage drain current VDS = 50 V; VIS = 0 V - 1 20 µA
IDSS Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C - 10 100 µA
RDS(ON) Drain-source on-state VIS = 5 V; IDM = 13 A; tp ≤ 300 µs; - 45 60 mΩ
resistance1 δ ≤ 0.01
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection2 Tmb = 25 ˚C; L ≤ 10 µH; RL = 10 mΩ
EDS(TO) Overload threshold energy VDD = 13 V; VIS = 5 V - 0.4 - J
td sc Response time VDD = 13 V; VIS = 5 V - 0.8 - ms
ID(SC) Drain current3 VDD = 13 V; VIS = 5 V - 45 - A
IDM(SC) Peak drain current4 VIS = 5 V; VDD = 13 V - 105 - A
Over temperature protection
Tj(TO) Threshold junction temperature VIS = 5 V; from ID ≥ 1 A5 150 - - ˚C
TRANSFER CHARACTERISTIC
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 10 V; IDM = 13 A tp ≤ 300 µs; 10 16 - S
δ ≤ 0.01
1 Continuous input voltage. The specified pulse width is for the drain current.
2 Refer to OVERLOAD PROTECTION LIMITING VALUES.
3 Continuous drain-source supply voltage. Pulsed input voltage.
4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd).
5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
June 1996 3 Rev 1.000
SYMBOL PAR C M T P. MAX. U T
VWO) Input threshold oItage VD5 = 5 V; |D : 1.0 1.5 2.0 V
I.S Input supply cu ent normal operatI V.S : 5 V 100 200 350 pA
v.S = 4 v . 160 270 pA
V.SR Protection rese oltage‘ T‘ = 25 'C 2.0 2.6 3.5 V
T‘ = 150 ‘C 1.0 . .
I.5L Input supply cu ent protection Iatch V.S = 5 V . 330 650 pA
v.S = 3.5 v . 240 430 pA
VIEWS Input breakdow voltage II = 10 mA 6 . . V
Ft.G Input series re ance T‘ = 25 'C . 33 kg
to gate 01 pow r MOSFET T‘ = 150 ‘C . 50 k9
SYMBOL
In an
I,
la DII
SYM L P C
IS 0 T
SYMB L P C M T P. MAX. U T
VSDO For IS _ . 1.0 1.5 V
t,, Rev not . .
SYMBOL P C M T M X. U T
Lu Intern Meas tab . 2.5 nH
to cen
Ls Intern Meas . 7.5 nH
solde pad
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA 1.0 1.5 2.0 V
IIS Input supply current normal operation; VIS = 5 V 100 200 350 µA
VIS = 4 V - 160 270 µA
VISR Protection reset voltage1 Tj = 25 ˚C 2.0 2.6 3.5 V
Tj = 150 ˚C 1.0 - -
IISL Input supply current protection latched; VIS = 5 V - 330 650 µA
VIS = 3.5 V - 240 430 µA
V(BR)IS Input breakdown voltage II = 10 mA 6 - - V
RIG Input series resistance Tj = 25 ˚C - 33 - kΩ
to gate of power MOSFET Tj = 150 ˚C - 50 - kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figure and test circuit.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
td on Turn-on delay time VDD = 13 V; VIS = 5 V - 17 - µs
trRise time resistive load RL = 2.1 Ω-75-µs
t
d off Turn-off delay time VDD = 13 V; VIS = 0 V - 60 - µs
tfFall time resistive load RL = 2.1 Ω-70-µs
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
ISContinuous forward current Tmb ≤ 25 ˚C; VIS = 0 V - 26 A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VSDO Forward voltage IS = 26 A; VIS = 0 V; tp = 300 µs - 1.0 1.5 V
trr Reverse recovery time not applicable2 ----
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
LdInternal drain inductance Measured from upper edge of tab - 2.5 - nH
to centre of die
LsInternal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
1 The input voltage below which the overload protection circuits will be reset.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
June 1996 4 Rev 1.000
’20 PD% Normalised Power Derailng
1 1o
mo
go
so
7o
so
so
Ao
3o
2o
1o
u 20 Au mo 120 140
2. Normalised power dissipation.
57% : roavPD/PD(25 ‘0) : f(T,,.b)
m zm (K/W) BUKiDErSODL
1
01
om ' '
1507 1505 15m 15m
Fig.5. Transient thermal impedance.
Zm W, = f{t); parameter D : tp/T
’20 lD% Normalised Current Derzrlng
r 10
mo
go
50
70
so
50
417
so
217
m
o
o 20 40 my 120 140
Fig.3. Normalised continuous drain current.
lD A BUK‘OQVSGDL
a t 4 5
Fig.6. T pical onrstate characteristics, 7', : 25 'C.
[13% 100le/iD(25 ’C) : HT”); conditions: V,S 5 V : NV“); parameter V,S; t‘7 : 2 ms
mm m a mu lA Bumaarsam ‘20 Hus mOhm some soDL
(rm/mud mu \ um \lmwv VIS l V
ma 3
WD 80
60
VD 40
I ms
to ms 20
moms
‘ ma
Fig.4. Safe operating area. Tm7 : 25 ‘C
iD & inM _ (VHS); IDM single pulse; parameter t‘7
a
a 40
Fig.7. Typical onrstate resistance, T : 25 ‘C.
RDSWN, : MD); parameter M5; t‘7 _ 2 m5
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
Fig.2. Normalised power dissipation.
P
D
% = 100
⋅
P
D
/P
D
(25 ˚C) = f(T
mb
)
Fig.3. Normalised continuous drain current.
I
D
% = 100
⋅
I
D
/I
D
(25 ˚C) = f(T
mb
); conditions: V
IS
= 5 V
Fig.4. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.5. Transient thermal impedance.
Z
th
j-mb
= f(t); parameter D = t
p
/T
Fig.6. Typical on-state characteristics, T
j
= 25 ˚C.
ID = f(V
DS
); parameter V
IS
; t
p
= 2 ms
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
IS
; t
p
= 2 ms
0 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07 1E-05 1E-03 1E-01 1E+01
t / s
Zth / (K/W)
10
1
0.1
0.01 0
0.5
0.2
0.1
0.05
0.02
BUK109-50DL
D =
D =
t
p
t
p
T
T
P
t
D
0 20 40 60 80 100 120 140
Tmb / C
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0 2 4
VDS / V
ID / A BUK109-50DL
50
40
30
20
10
0 135
VIS / V = 6
5.5
5
4.5
4
3.5
3
1 100
VDS / V
ID & IDM / A
1000
100
10
1
DC
BUK109-50DL
10
RDS(ON) = VDS/ID
Overload protection characteristics not shown
100 us
1 ms
10 ms
100 ms
tp =
0 20 40
ID / A
RDS / mOhm BUK109-50DL
120
100
80
60
40
20
0
VIS / V =
4.5 55.5 6
4
3.5
June 1996 5 Rev 1.000
a Normalised RDS ON 7 1
o
750 w 720 a 50 100 120 140
Fig.8. Normalised drain7source on7state resistance.
a : Hus,o~,/RDS,ON,25 '0 : rm: ID 7 13 A: \/,5 7 5 v
BUKwBrSODL
Energy & Tme
05
o
760 720 20 MD 180 220
Fig.1 1. Typical overload protection characteristics.
Conditions. VDD7 _ 13 V V,s7 _ 5 V 80 load 30 m9
l .
100 td sc ms BUKHJQ 50m
10
1
01
01 10
Fig.9. Ty I‘cal overload protection characteristics.
rm : i P05); conditions: V,S 2 4 V; T : 25 ‘C.
an ID A BUKlDSrSGDL
20
m
a
50 70
Fig. 12. pica/clamping charactensncs. 25 ‘.C
in : [(VD/S) conditions. \/,5 : 0 V; t < 50="" us="" pnsm="" 120="" um="" an="" an="" au="" 2n="" a="" ran="" «m="" 720="" a="" an="" um="" 120="" mu="" fig.="" 10.="" normalised="" limiting="" overload="" dissipation.="" posm%="" 100pdsm/pdsm(25="" 0}="" ’(tmbl="" vlsltdl="" i="" v="" o="" 750="" 7w="" 2n="" 0="" so="" 100="" 120="" we="" fig.="" 13.="" input="" threshold="" voltage.="" [(77);="" conditions:="" in="" :="" 1="" ma;="" vd="" 5="" v="" visqu="">Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
Fig.8. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)
25 ˚C = f(T
j
); I
D
= 13 A; V
IS
= 5 V
Fig.9. Typical overload protection characteristics.
t
d sc
= f(P
DS
); conditions: V
IS
≥
4 V; T
j
= 25 ˚C.
Fig.10. Normalised limiting overload dissipation.
P
DSM
% =100
⋅
P
DSM
/P
DSM
(25 ˚C) = f(T
mb
)
Fig.11. Typical overload protection characteristics.
Conditions: V
DD
= 13 V; V
IS
= 5 V; SC load = 30 m
Ω
Fig.12. Typical clamping characteristics, 25 ˚C.
I
D
= f(V
DS
); conditions: V
IS
= 0 V; t
p
≤
50
µ
s
Fig.13. Input threshold voltage.
V
IS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= 5 V
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
aNormalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
-60 -20 20 60 100 140 180 220
Tmb / C
BUK109-50DL
1
0.5
0
Energy / J
Time / ms
Tj(TO)
Energy & Time
0.1 1 10
PDS / kW
td sc / ms BUK109-50DL
100
10
1
0.1
PDSM
50 60 70
VIS / V
ID / A BUK109-50DL
30
20
10
0
typ.
-60 -40 -20 0 20 40 60 80 100 120 140
Tmb / C
PDSM%
120
100
80
60
40
20
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VIS(TO) / V
2
1
0
max.
typ.
min.
June 1996 6 Rev 1.000
sun IISL&iISiuA EUKmQ 50m vuswavnsw BuKtuBVSDDL
sun CTiON LATCHED was
m
400
HSL \
300 RE
\ / us 5
200
i / x
‘00 NORMALi u
a ‘ a 200 am)
a 4 s
Fig. 14. Typical DC input characteristics. T : 25 ’C.
ASL & 1,5 : f( V15)? protection latched & norma/ operation
Fig. 17. Typical switching waveforms, resistive load.
Von: 13 V,‘HL:2.1Q,‘FI,:50§2, 77:25 '0.
is A BUKIDQVSDDL
we
so
u
u 2
Fig. 15. Typical reverse diode current. T, : 25 ”C.
Is = fiVSDS); conditions: \/,S : a V
EDSM‘V:
120
i 10
i no
90
so
70
so
50
40
30
2o
10
o 20 40 me 120 Mo
Fig. 18. Normalised clamping energy rating.
[Em/1% : liTmb); conditions: lD : 26 A; V,S : 5 V
DD
measure
:2 av
0R1
Fig. 16. Test circuit [or resistive load switching times.
Vic
Fig. 19. Clamping energy test circuit, Fl,S : 50 9.
Elm : 05 ' L “Wt-ms: ’ Vim)
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
Fig.14. Typical DC input characteristics, T
j
= 25 ˚C.
I
ISL
& I
IS
= f(V
IS
); protection latched & normal operation
Fig.15. Typical reverse diode current, T
j
= 25 ˚C.
I
S
= f(V
SDS
); conditions: V
IS
= 0 V
Fig.16. Test circuit for resistive load switching times.
Fig.17. Typical switching waveforms, resistive load.
V
DD
= 13 V; R
L
= 2.1
Ω
; R
I
= 50
Ω
, T
j
= 25 ˚C.
Fig.18. Normalised clamping energy rating.
E
DSM
% = f(T
mb
); conditions: I
D
= 26 A; V
IS
= 5 V
Fig.19. Clamping energy test circuit, R
IS
= 50
Ω
.
0 2 4 6
VIS / V
IISL & IIS / uA BUK109-50DL
600
500
400
300
200
100
0
RESET
PROTECTION LATCHED
NORMAL
IISL
IIS
0 200 400 600
time / us
VIS / V & VDS / V BUK109-50DL
15
10
5
0
VIS
VDS
0 20 40 60 80 100 120 140
Tmb / C
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
012
VSD / V
IS / A BUK109-50DL
100
50
0
L
D.U.T.
VDD
RIS R 01
VDS
-ID/100
+
-
shunt
VIS
0
P
D
S
I
TOPFET
ID
0
VDS
0
VDD
V(CL)DSS
Schottky
VDD
D.U.T.
R
0V
0R1
I
VIS
ID measure
D
S
I
TOPFET
P
RL
EDSM =0.5 ⋅LID
2⋅V(CL)DSS/(V(CL)DSS −VDD)
June 1996 7 Rev 1.000
ldss
“mm:
mm:
mm
mom:
0 20 A0 mo 120 Ma
Fig.20. Typical oflrstale leakage current.
lass : f(T,); Conditions: VDS : 40 V; [,5 : 0 V.
llsu ac hsl nnrmahsed
‘5
a 5
750 20 20 on NO IED
Fig.21. Normalised input currents (normal & latched).
Asa/$0250 & 1,5L/Im25'c : rm: V/s = 5 v
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
Fig.20. Typical off-state leakage current.
I
DSS
= f(T
j
); Conditions: V
DS
= 40 V; I
IS
= 0 V. Fig.21. Normalised input currents (normal & latched).
I
ISO
/I
ISO
25˚C & I
ISL
/I
ISL
25˚C = f(T
j
); V
IS
= 5 V
0 20 40 60 80 100 120 140
Tj / C
Idss
1 mA
100 uA
10 uA
1 uA
100 nA
typ.
-60 -20 20 60 100 140 180
Tj / C
Iiso & Iisl normalised to 25 C
1.5
1
0.5
June 1996 8 Rev 1.000
Dimensions in mm
Net Mass: 1.4g :1 :1;
[1 1 2 91—1
1 1 L 2
3 HH 41 *
|:|’1 3‘1
Fig.22. SOT404 .‘ centre pin connected to mounting base.
Dimensions in mm
Fig.23. SOT404 : minimum pad sizes [or surface mounting.
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.22. SOT404 : centre pin connected to mounting base.
Notes
1. Epoxy meets UL94 V0 at 1/8".
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.23. SOT404 : minimum pad sizes for surface mounting
.
Notes
1. Plastic meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
June 1996 9 Rev 1.000
Data sheet status
_.
Objective specification
_.
Preiiminary specification
Product specilication T
Li iting values
Limiting values are given in
or more of the iimiting valu
operation ol the device at t
this specification is not imp
Application information
Where application inlormat
© Philips Electronics N.V
All rights are reserved. Re
copyright owner.
The information presented
accurate and reliabie and m
consequence of its use. P
industrial or inteiIectuaI pro
Philips Semiconductors Product specification
PowerMOS transistor BUK109-50DL
Logic level TOPFET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
June 1996 10 Rev 1.000
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