Silicon I: : II
ce V
A
' Fl
ts use the latest PIN DESCRIPTION
chnology to —
est possible 1 gate
e in each I
age rating. 2 drain
3 source
rs
er supplies tab drain a
is supplied in
conventional
SYMBOL PA C
VD55 Drainrsourc age T‘ : 25 ‘C to , 150 V
VDGR Drainrgate v e T‘ : 25 ‘C to , 150 V
VGS Gatersource ge , 1 20 V
|D Continuous current Tmb : 25 ‘C , 73 A
Tmb : 100 'C , 51 A
|DM Pulsed drai ent Tmb : 25 ‘C , 290 A
PD Total power pation Tmb : 25 ‘C , 300 W
T‘, Tslg Operating ju n and , 55 175 'C
storage tern ure
SYMBOL P C
EAS Nonrrep che Unclam A; , 707 ml
energy ra : 100 250;
VDD S 25 refer to
fig:15
|AS Nonrrep che , 73 A
current
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance VDSS = 150 V
• Fast switching
• Low thermal resistance ID = 73 A
RDS(ON) ≤ 20 mΩ
GENERAL DESCRIPTION PINNING SOT429 (TO247)
SiliconMAXproducts use thelatest PIN DESCRIPTION
Philips Trench technology to
achieve the lowest possible 1 gate
on-state resistance in each
package at each voltage rating. 2 drain
Applications:- 3 source
• d.c. to d.c. converters
• switched mode power supplies tab drain
The PSMN020-150W is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 150 V
VDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ- 150 V
VGS Gate-source voltage - ± 20 V
IDContinuous drain current Tmb = 25 ˚C - 73 A
Tmb = 100 ˚C - 51 A
IDM Pulsed drain current Tmb = 25 ˚C - 290 A
PDTotal power dissipation Tmb = 25 ˚C - 300 W
Tj, Tstg Operating junction and - 55 175 ˚C
storage temperature
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 73 A; - 707 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to
fig:15
IAS Non-repetitive avalanche - 73 A
current
d
g
s
23
1
November 1999 1 Rev 1.000
Silicon 1'1 : II
SYMBOL P C
Rm,”b Therm tion , 0.5 K/W
to me
Rm,a Therm tion in fre 45 K/W
to am
SYMBOL PARAMETER C M N. TYP. M X. U T
VampSS Drainrsource breakdcwn VGS : 0 V; ID 150 , , V
voltage T‘ : 755'0 134 , , V
Vesm, Gate threshold voltage VDS : V65; |D 2.0 3 0 4.0 V
T‘ : 175'C 1.0 . . v
T1: 550 . . e v
Ram," Drainrsource cnrstate VGS : 10 V; | 12 20 m0
resistance T‘ : 175'C , 56 m0
IGSS Gate source leakage current VGS : :10 V; 2 100 nA
|DSS Zerc gate voltage drain VDS : 150 V; 0.05 10 uA
current T‘ : 175'C , 500 uA
CtEM Total gate charge |D _ 227 , nC
g5 Gaterscurce charge 46 , nC
CtEd Gaterdrain (Miller) charge 91 , nC
td m Turnron delay time VDD _ 34 , ns
t, Turnron rise time VGS _ 79 , ns
Id .211 Turnrpff delay time Resis 233 , ns
t Turnrpff fall time 101 , ns
Lfl Internal drain inductance Meas 3.5 , nH
Lfl Internal drain inductance Meas 1 die 4.5 , nH
Ls Internal source inductance Meas 7.5 , nH
bond
Cm; Input capacitance V55 9537 , pF
Cm Output capacitance 854 , pF
Cyss Feedback capacitance 380 , pF
SYMBOL P c M N. TYP. M x u T
|S Continu urrent , 73 A
(body d
|SM Pulsed t (body , 290 A
diode)
VSD Diode to e |F _ 25 A 0.85 1.2 V
IF _ 75 A 1.1 . v
t" Re IF = 127 ns
Q,, Re v6 1 0 ac
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction - 0.5 K/W
to mounting base
Rth j-a Thermal resistance junction in free air 45 - K/W
to ambient
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 150 - - V
voltage Tj = -55˚C 134 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V
Tj = 175˚C 1.0 - - V
Tj = -55˚C - - 6 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 12 20 mΩ
resistance Tj = 175˚C - - 56 mΩ
IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
IDSS Zero gate voltage drain VDS = 150 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Qg(tot) Total gate charge ID = 73 A; VDD = 120 V; VGS = 10 V - 227 - nC
Qgs Gate-source charge - 46 - nC
Qgd Gate-drain (Miller) charge - 91 - nC
td on Turn-on delay time VDD = 75 V; RD = 2.7 Ω; - 34 - ns
trTurn-on rise time VGS = 10 V; RG = 5.6 Ω-79-ns
td off Turn-off delay time Resistive load - 233 - ns
tfTurn-off fall time - 101 - ns
LdInternal drain inductance Measured from tab to centre of die - 3.5 - nH
LdInternal drain inductance Measured from drain lead to centre of die - 4.5 - nH
LsInternal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 9537 - pF
Coss Output capacitance - 854 - pF
Crss Feedback capacitance - 380 - pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ISContinuous source current - - 73 A
(body diode)
ISM Pulsed source current (body - - 290 A
diode)
VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V
IF = 75 A; VGS = 0 V - 1.1 - V
trr Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 127 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 30 V - 1.0 - µC
November 1999 2 Rev 1.000
Silicon ll : II
Normalised Power D
mo
so
so
70
so
so
40
so
20
m
D 25 50 125 150 I75
Mounting Ease (emperzlure, Tmh (C)
Fig. 1. Normalised power dissipation.
PD% : mam/PM5 a: firm)
‘ Translzm manual m. h
n :05
n.2
0.1 m
Mn
ANTH»
mm
was 1:425 IE 1am 1am 1mm
5)
Fig.4. Transient thermal impedance.
2mm = lit); parameter D : tV/T
Normalised Current
um
90
an
m
an
50
an
an
20
m
n 25 an 125 150 175
Mourning Base temperature, Tm!) ((2)
Fig.2. Normalised continuous drain current.
10% : wall/1025.0: firm); v65 2 10 V
mam Curve ID A
n:25c ves I
an
70
so
so
an
an
20
m
n
n 0.2 0.4 0.5 u
Dram vnsm
Fig.5. Typical output characteristics, T/ : 25 'C.
IS LE 2
Peak Pulsed Dram c
mnn
RDSlom : VDSJ ID
Inn
m
I
1 m Inn mnn
Dram vns iVi
Fig.3. Safe operating area
iD & IBM : f(VDS); IDM single pulse; parameter t‘7
nmmsoum On Res onmsi
4.2 v u v
4.5 v
Mv
ans
um;
um
ans
ans
um
nna
n02 ev
am
0
av/ ves:mv
n m 2n n so 70 an
Dr
Fig.6. Typical onrstate resistance, T, : 25 ‘C.
RosicNi = flip)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); V
GS
≥
10 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0.001
0.01
0.1
1
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02 tp D = tp/T
D
P
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0
10
20
30
40
50
60
70
80
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
4.4 V
Tj = 25 C VGS = 10V
4.6 V
4.8 V
5 V
8 V
4.2 V
5.2 V
6 V
1
10
100
1000
1 10 100 1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 1020304050607080
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
5V
8 V
4.2 V
4.6 V
4.8 V
4.4V
6 V
5.2V
November 1999 3 Rev 1.000
Silicon ii : II
Dram cunem. ID (Ab
inn
an
in
7n
5n
5n
in
an
2n
in
n
vos ) ID x Rosiom
nn.51152 44555.55
Gale vesivi
Fig. 7. Typical transfer characteristics.
5 Threshold Vuliage, v
maximum
typical
minimum
so 40 -2o 0 2n 100 120 no ‘50 mo
.iunciiun Temperature. T] (ci
Fig. 10. Gate threshold voltage.
VGWO, _ f(T,); conditions: lD : 1 mA,‘ VDS _ VGS
rrauscouauciance. g
was > ID x Rosin"
ioo
o 10 2:2 an 0 m an an inn
Dram cuneui. ID (Ab
Fig.8. Typical transconductance, T, : 25 ”C.
ma“ Drain currenl. ID
1.0E-D2
LOE-DS
LOE-M
maximum
LOE-DS
LOE-DG
o n.5 i i a 3.5 4 4.5 5
Gale»snuvce vuliage, vcs m
Fig. 11. Subrthresho/d drain current.
ID : f(VGSV,; conditions: T, : 25 ‘C
Normalised On-slale
m an -2u n zu
Junction temperature. T] (op
‘00 120 no ‘50 130
Fig. 9. Normalised drainrsource onrstate resistance.
Roman/Romania 'c — (77)
Ca nuances. Cis i
moooo ”3
mono
um
um
0.1 i um um
Dla e,vos (Vi
Fig. 12. Typical capacitances, 0,55, CD55, 0,55.
C _ [(VDS); conditions: VGS : 0 V; f: 1 MHz
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Threshold Voltage, VGS(TO) (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
typical
maximum
minimum
0
10
20
30
40
50
60
70
80
90
100
0 102030405060708090100
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
minimum
typical
maximum
Normalised On-state Resistance
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
100
1000
10000
100000
0.1 1 10 100 1000
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
November 1999 4 Rev 1.000
Silicon it : II
u
Fig.1.}. Typical tumrcn gatercharge characteristics.
Galesuuice vuilage, ve
ID:73A
1|:2sc
vun:|2nv
n 25 so 75 I 5:: 175 m 225 25a
ca ("Ci
VGs = [(06)
Maximum Avalanche 0
mm
m
nche:15flc
n I
mum 0m 1 m
Ava Av mm
Fig. 15. Maximum permissible nonrrepet/‘tive
avalanche current (IAS) versus avalanche time (IN);
unclamped inductive load
SuurczrDiaIn Dlofle c
v:n
n n.1 n.2 as n
Scum VSDSW)
0.: 0.9 I 1.1 1.2
Fig.14. Typical reverse diode current.
l; _ f{|/SDS); conditions: VGS : U V; parameter T,
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
AV
);
unclamped inductive load
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0 25 50 75 100 125 150 175 200 225 250
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 73A
Tj = 25 C
VDD = 30 V
VDD = 120 V
0.1
1
10
100
0.001 0.01 0.1 1 10
Avalanche time, tAV (ms)
Maximum Avalanche Current, IAS (A)
Tj prior to avalanche = 150 C
25 C
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
November 1999 5 Rev 1.000
Silicon I: ‘ II
Plastic single-Ended lhrough»hol2 package: heatslnk
unted: I mounting holg: (Maid T041” SOT429
Eu mu m
mMiNswoNMmm m mum mmmmx)
UNIYAA‘bb‘bichia umpuqnswvfln
52 ‘9 ‘2 12 :2 us 2‘ m on u 25 u. 75 m w w
mm 0? ‘T US Hz 2H Ub 20 ‘5 5‘5 )5 JJ 24 51 1:; H 0‘ ‘5) v ‘2”
Non
‘ mm a, («mum‘s me mmuea mm m u
firmness
0mm: :unopm
"“5“" \Ec muse PROJECDON ‘55“ WE
, W
sonze m 247 a @ w M m
Fig. 16. SOT429; pin 2 connected to mounting base
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
MECHANICAL DATA
Fig.16. SOT429; pin 2 connected to mounting base
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT429 envelope.
3. Epoxy meets UL94 V0 at 1/8".
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT429 TO-247 98-04-07
99-08-04
0 10 20 mm
scale
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429
E
P
A
A1
β
w
M
b
12 3
ee
b1
b2
c
Q
q
L
Y
R
D
S
L1
(1)
α
UNIT A1D
bEewSRqQPLY
b2
b1cL1
(1)
DIMENSIONS (mm are the original dimensions)
Aβ
α
mm 17°
13°
6°
4°
5.3
4.7 1.9
1.7 2.2
1.8
1.2
0.9 3.2
2.8 0.9
0.6 21
20 16
15 5.45 3.7
3.3 2.6
2.4 5.3 7.5
7.1 0.4 15.7
15.3
16
15 4.0
3.6 3.5
3.3
Note
1. Tinning of terminals are uncontrolled within zone L1.
November 1999 6 Rev 1.000
Silicon ii : II
Data sheet status
Objective specification Th
Preiimihary specification Th
Product specilication Th
Li ting values
Limiting values are given in a
or more of the iimitihg values
operation oi the device at the
this specification is not implie
one
of
Application information
Where application ihlormatio
© Philips Electronics N.V.1
All rights are reserved. Repr
copyright owner.
The information presented in
accurate and reliabie and ma
consequence of its use. Pub
industrial or inteiIectuaI prope
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN020-150W
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1999 7 Rev 1.000
Products related to this Datasheet
MOSFET N-CH 150V 73A SOT429