Supports 100-MHz bus for Pentium and PowerPCTM operations with zero wait states Fully registered inputs and outputs for pipelined operation by 18 common I/O architecture 3.3V core power supply / 3.3V I/O operation Fast clock-to-output times 3.5 ns (for 166-MHz device) 4.0 ns (for 133-MHz device) 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100 TQFP pinout "ZZ" Sleep Mode option and Stop Clock option The WCSS0418V1P I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise ns (166-MHz device). The WCSS0418V1P supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[1:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.

The by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.

-166 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial

119-Ball BGA VDDQ NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC VDDQ A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A NC VSS BWb VSS NC VSS Vss VSS MODE NC 4 ADSP ADSC VDD CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC VSS Vss VSS NC VSS BWa VSS CE3 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC 7 VDDQ NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ

Name A[17:0] Description Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be Synchronous asserted LOW to conduct a byte write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select/deselect the device. ADSP is ignored CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically increSynchronous ments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0] Synchronous is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. I/O InputSynchronous