High Speed (Equal Access and Cycle Times) 10/12/15/20/25/35 ns (Commercial) /35 ns (Military) CMOS for Low Power 495 mW Max. � 10/12/15/20/25 (Commercial) 495 mW Max. � 15/20/25/35 (Military) Single 5V�10% Power Supply Separate I/O Fully TTL Compatible Inputs and Outputs Resistant to single event upset and latchup resulting from advanced process and design improvements Standard 22-pin 400 mil DIP, 24-pin 300 mil SOIC, 24-pin LCC package and 24-pin CERPACK package

The a 1,024-bit high-speed (10ns) Static RAM with x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and active HIGH chip select two (CS 2) as well as 3state outputs. In addition to very high performance and very high density, the device features latch-up protection, single event and upset protection. The P4C422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24pin 300 mil SOIC, 24-pin LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges.

Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value 0.5 to VCC to +125 Unit V Symbol TBIAS TSTG �C I OUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value +150 20 Unit �C mA

P4C422 Symbol VOH VOL VIH VIL VCL I OS Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Clamp Diode Voltage Input Load Current Output Current (High Z) Output Short Circuit Current(3) IIN �10 mA GND VIN VCC VOL VOUT VOH , Output Disabled VCC= Max., VOUT = GND Test Conditions IOH = �5.2 mA, VCC = Min. IOL = +8 mA, VCC = Min. 2.1 0.8 Min 2.4 0.4 Max Unit �A mA

Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested.

5. Transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input and output levels of 1.5V. The output loading is equivalent to the specified IOL/IOH with a load capacitance as in Fig. 1a and 1b respectively. 6. Transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see Fig 1d. Transition is measured at steady state HIGH level -500mV or steady state LOW level +500mV on the output from a level on the input with load shown in Fig. tW is measured at tWSA = min.: tWSA is measured tW = min.

An active LOW write enable (WE) controls the writing/ reading operation of the memory. When the chip select one (CS 1) and the write enable (WE) are LOW and the chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the "write recovery glitch." Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW.

Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state for the P4C422.

Parameter Read Cycle Time (5) Chip Select Time (5) Chip Select to High-Z (6) Output Enable Time Output Enable to High-Z Address Access Time (5)