FEATURES SUMMARY s The �PSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core The �PSD3200 Family of Flash PSDs features dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and one External Interrupt. As with other Flash PSD families, the �PSD3200 Family is also in-system programmable (ISP) via a JTAG ISP interface. Large 8 KByte SRAM with battery back-up option Dual bank Flash memories � 128 KByte or 256 KByte main Flash memory � 32 KByte secondary Flash memory

Content Security � Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories. High-speed clock standard 8032 core (12-cycle) USB Interface (�PSD3234A-40U6 only) I2C interface for peripheral connections Five Pulse Width Modulator (PWM) channels Standalone Display Data Channel (DDC) Six I/O ports with to 50 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage 3.6 V

SUMMARY DESCRIPTION s Dual bank Flash memories � Concurrent operation, read from memory one while erasing and writing the other. In-Application Programming (IAP) for remote updates � Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces � Large 32 KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation � Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks

� One 16-bit PWM unit Standalone Display Data Channel (DDC) � For use in monitor, projector, and TV applications � Compliant with VESA standards DDC1 and DDC2B � Eliminate external DDC PROM Six I/O ports with to 50 I/O pins � Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG � Eliminates need for external latches and logic

3000 gate PLD with 16 macrocells � Create glue logic, state machines, delays, etc. � Eliminate external PALs, PLDs, and 74HCxx � Simple PSDsoft Express software...Free

Large SRAM with battery back-up option � 8 KByte SRAM for RTOS, high-level languages, communication buffers, and stacks

Programmable Decode PLD for flexible address mapping of all memories � Place individual Flash and SRAM sectors on any address boundary � Built-in page register breaks restrictive 8032 limit of 64 KByte address space � Special register swaps Flash memory segments between 8032 "program" space and "data" space for efficient In-Application Programming

Supervisor functions � Generates reset upon low voltage or watchdog time-out. Eliminate external supervisor device � Reset In pin

In-System Programming (ISP) via JTAG � Program entire chip - 25 seconds with no involvement 8032 � Allows efficient manufacturing, easy product testing, and Just-In-Time inventory � Eliminate sockets and pre-programmed parts � Program with FlashLINKTM cable and any PC

High-speed clock standard 8032 core � 40 MHz operation V, 24 MHz V � Two UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts

USB Interface (�PSD3234A-40U6 only) � Supports USB 1.1 Slow Mode (1.5 Mbit/s) � Control endpoint 0 and interrupt endpoints 1 and 2

I2C interface for peripheral connections � Capable of master or slave operation Five Pulse Width Modulator (PWM) channels � Four 8-bit PWM units

Packages � 52-pin TQFP � 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals

Port I2C 3 Timer / Counters 256 Byte SRAM 4 Channel ADC USB DDC PWM Reset Logic w/ 256 Byte & 5 Channels LVD & WDT SRAM Transceiver

MCU MODULE 8032 Internal Bus A0-A15 RD,PSEN WR,ALE PSD MODULE Page Register Decode PLD or 2Mb Main Flash 256Kb Secondary Flash 64Kb SRAM Bus Interface D0-D7 Reset Port 0, 2 Ext. Bus