Instant-on - Powers up in microseconds via on-chip E2CMOS� based memory No external configuration memory Excellent design security, no bit stream to intercept Reconfigure SRAM based logic in milliseconds

True PLL technology to 320MHz operation Clock multiplication and division Phase adjustment Shift clocks in 250ps steps

to 1.25M system gates to 496 I/O 1.8V, 2.5V, and 3.3V VCC operation to 414Kb sysMEMTM embedded memory

High speed memory support through SSTL and HSTL Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL Standard logic supported through LVTTL, LVCMOS 3.3, 2.5 and 1.8 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces Programmable drive strength for series termination Programmable bus maintenance

Four LUT-4 per PFU supports wide and narrow functions Dual flip-flops per LUT-4 for extensive pipelining Dedicated logic for adders, multipliers, multiplexers, and counters

Multiple sysMEM Embedded RAM Blocks � Single port, Dual port, and FIFO operation 64-bit distributed memory in each PFU � Single port, Double port, FIFO, and Shift Register operation

ispXPGA 125/E System Gates PFUs LUT-4s Logic FFs sysMEM Memory Distributed Memory EBR sysHSI Channels User I/O Packaging

to 800Mbps performance to 20 channels per device Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)

� 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either reprogrammable or non-volatile. This family couples this capability with a mainstream architecture containing the features required for today's system-level design. The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost "E-Series" supports the same high-performance FPGA fabric without the sysHSI Block. Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applications. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry standard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIGTM peripheral port. The family spans the density and I/O range required for the majority of today's logic designs, to 1.25M system gates and to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, providing easy integration into the overall system. System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are supported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization (SERDES). The ispLEVERTM design tool from Lattice allows easy implementation of designs using the ispXPGA product. Synthesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor planning and the management of other constraints within the device. The tool also provides outputs to common timing analysis tools for timing analysis. To increase designer productivity, Lattice provides a variety of pre-designed modules referred as IP cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces, and memory controllers. Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide designers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz. Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly used by logic designers. Table 2. ispXPGA Speed Performance for Typical Building Blocks

Function 8:1 Asynch MUX 1:32 Asynch Demultiplexer 8 2-LL Pipelined Multiplier 32-bit Up/Down Counter 32-bit Shift Register Performance 150 MHz 125 MHz 225 MHz 290 MHz 360 MHz

The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units (PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distributed throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to easily implement their designs, since any logic function can be placed in any section of the device. The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently. The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic elements for fast access to combinatorial functions. The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other storage types. They are designed to facilitate both single and dual-port memory for high-speed applications. These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs. The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices without the need for external transceivers. The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data to 800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery (CDR) logic. The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for each global clock tree in the device.