LFX500C-3F900C of Lattice ispXPGA Family

LFX500C-3F900C FPGAs Overview

The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either reprogrammable or non-volatile. This family couples this capability with a mainstream architecture containing the features required for today’s system-level design.

The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the sysHSI Block.

Electrically Erasable CMOS (E2 CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applications. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2 CMOS cells can be programmed and verified through the IEEE 1532 industry standard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG peripheral port.

The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M system gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, providing easy integration into the overall system.

System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are supported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization (SERDES).

The ispLEVER design tool from Lattice allows easy implementation of designs using the ispXPGA product. Synthesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor planning and the management of other constraints within the device. The tool also provides outputs to common timing analysis tools for timing analysis.

To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces, and memory controllers.

Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide designers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz. Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly used by logic designers.

Features

■ Non-volatile, Infinitely Reconfigurable

• Instant-on - Powers up in microseconds via on-chip E2 CMOS based memory

• No external configuration memory

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

■ High Logic Density for System-level Integration

• 139K to 1.25M system gates

• 160 to 496 I/O

• 1.8V, 2.5V, and 3.3V VCC operation

• Up to 414Kb sysMEM embedded memory

■ High Performance Programmable Function Unit (PFU)

• Four LUT-4 per PFU supports wide and narrow functions

• Dual flip-flops per LUT-4 for extensive pipelining

• Dedicated logic for adders, multipliers, multiplexers, and counters

■ Flexible Memory Resources

• Multiple sysMEM Embedded RAM Blocks

– Single port, Dual port, and FIFO operation

• 64-bit distributed memory in each PFU

– Single port, Double port, FIFO, and Shift Register operation

■ Flexible Programming, Reconfiguration, and Testing

• Supports IEEE 1532 and 1149.1

• Microprocessor configuration interface

• Program E2 CMOS while operating from SRAM

■ Eight sysCLOCK Phase Locked Loops (PLLs) for Clock Management

• True PLL technology

• 10MHz to 320MHz operation

• Clock multiplication and division

• Phase adjustment

• Shift clocks in 250ps steps

■ sysIO for High System Performance

• High speed memory support through SSTL and HSTL

• Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL

• Standard logic supported through LVTTL, LVCMOS 3.3, 2.5 and 1.8

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces

• Programmable drive strength for series termination

• Programmable bus maintenance

■ Two Options Available

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

■ sysHSI Capability for Ultra Fast Serial Communications

• Up to 800Mbps performance

• Up to 20 channels per device

• Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)

FAQ

Q: Does the price of LFX500C-3F900C devices fluctuate frequently?
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No, only submit the quantity, email address and other contact information required for the inquiry of LFX500C-3F900C, but you need to sign up for the post comments and resource downloads.
Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice LFX500 Development Boards, Evaluation Boards, or ispXPGA Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain LFX500C-3F900C technical support documents?
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Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the LFX500C-3F900C pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.