Low input and output leakage 1� A (max.) Extended commercial range to +85�C CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Available in PDIP, SOIC, SSOP, and QSOP packages B, C and D speed grades High drive outputs (-15mA IOH, 48mA IOL) Power off disable outputs permit "live insertion"

The FCT823T series is built using an advanced dual metal CMOS technology. The FCT823T series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) � ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823T high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for lowcapacitance bus loading in high-impedance state.

Symbol VTERM(2) VTERM(3) TSTG IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. to +120 Unit �C mA

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Outputs and I/O terminals only.

Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF

Names DI CLR I/O I Description The D flip-flop data inputs. When the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-to-HIGH transition. The register 3-state outputs. Clock Enable. When the clock enable is LOW, data on the DI input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the YI outputs are in the high-impedance state. When the OE input is LOW, the TRUE register data is present at the YI outputs.

Symbol VIH VIL II L IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State Output Pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min., IIN = �18mA

Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. = 0.5V

Symbol VOH VOL IOS IOFF Parameter Output HIGH Voltage Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL VCC = Max., = GND(3) VCC = 0V, VIN mA �A Test Conditions(1) IOH = �8mA IOH = �15mA IOL = 48mA Min. 3 0.3 Max. 0.5 V Unit V

NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc 5.0V, +25�C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter �55�C. 5. This parameter is guaranteed but not tested.